Attached is a question with my answer. This is a 2's complement converter which I designed. My problem is the MSB output because I had to eliminate an XOR gate in the input for the graph to match my truth table. Any help would be much appreciated.

 

I think your circuit is correct. But the exercise asks you to make a circuit for 3 bits + sign not 4 +sign. Not that it is a mistake or anything...

 

Oki.. I did the fourth half adder to check the overflow. Thanks I check it again.