So..

This is my diagram and i need to meet a few specs:
1) must be at least 20k Input resistance (which mine comes out to about 22k if i did the calculations correct)
2) total gain of at least 50 (i calculated this to be -93.93 so I should be fine on that)

These are my two main concerns:
3) should work with an AC input voltage of 1 mV (I tried simulating this on Pspice but I can't even get an output..)
4)voltage gain must be > 50 for frequencies 20-20kHz..

Firstly I dont know what the value of Beta is.. So I just guessed it to be around 156 by using a simple BJT circuit... I think i have to use that graph of Ic vs Ib and the line Vcc/Rc but I don't really know how to produce that graph.. but thats not as important as getting the biases correct

I plan on replacing the current sources with current mirrors, because if Ie is positive in that direction then we know the BJTs are active.. Unless someone has a better ideas instead of making it super messy with current mirrors, how would I go about biasing that circuit to make all 3 BJTs in active mode? My calculations were all right I believe but I can't seem to get the right output on PSPICE. If someone could give me a hint or help me out i'd really appreciate it..

 

, how would I go about biasing that circuit to make all 3 BJTs in active mode? .

Answer to that question alone.

Using your second stage as an example. Since it has a emitter resistor.

Voltage at the collector (VC) is (VCC/2) or 4.5v.

4.5v. / 5K = 0.9mA = IC

0.9mA x 1K = 0.9v. = VE

0.9v + 0.7v = 1.6v. = VB


using your value of 100K for the bleeder resistor to ground, then the current thru this resistor will be,

1.6v. / 100K = 16uA.

the top resistor connected to the supply from the base is, then

(9v. - 1.6v) / 16uA. = 462.5K make it nominal 470K.

Note:
the 100K is probably to big so it may cause the VC to be low output, lower than 4.5v. because the base current is loading the divider.

thats how you bias it at the base.

If the VC is too low, then make the bottom (bleeder) resistor 10 x RE or 10K ohms.

then 1.6v. / 10K = 160uA.

and the top resistor will be

(9v - 1.6v.) / 160uA = 46.5K make it 47K nominal value.

And see if the VC is closer to 4.5v.

That will get your transistor in the active linear region.

 

If the load is the 50 ohms resistor then the emitter-follower (the 3rd transistor) cannot drive it.

 

What exactly are the design specifications? I take it they are:

Rout = 50 ohms (is this correct?)
Rin >= 20 kohms
Total gain, Av >= 50V/V
Vin = 1mV
Midband range: 20Hz -20kHz (Is this spec giving you the exact roll on and roll off frequencies? Or is this range just a minimum requirement?)
Are there any more specs to be met?

Forget the current mirrors if you don't have to use them. Keep it simple. Your first stage should be an emitter follower, the second stage a CE amp and the output stage a differential pair.

More if you want it.