# Multiplexers

Discussion in 'Homework Help' started by Jackal, Oct 26, 2008.

1. ### Jackal Thread Starter New Member

Oct 26, 2008
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0
I am just starting to learn about MUXes and how they work. I've been understanding everything up to this point.

The problem says:
Implement a full adder using two 8-to-1 MUXes. Connect X, Y, and Cin to the control inputs of the MUXes and connect 1 or 0 to each data input.

This is what I came up with for a drawing. When I look at it though, it seems to me that it is more of a Half-Adder rather than a full since it only has 2 "inputs" I guess you would call it instead of 3 like a full adder would have.

Can I get help on what I have done so far?

http://img340.imageshack.us/my.php?image=8to1muxfulladdercircuitqp0.jpg If the image doesn't show up.

2. ### beenthere Retired Moderator

Apr 20, 2004
15,808
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All the inputs are the same. What is the output supposed to be for each address selection?

3. ### Jackal Thread Starter New Member

Oct 26, 2008
4
0
If all the inputs are the same then the output will be the same as the inputs. (If we are just talking about 1 multiplexer.)
So if all the inputs are 1, the only possible outcome for the output is 1 (and vice versa for 0).
Maybe I don't understand how that helps me solve the problem. I just assigned 0's or 1's to each input not in any specific order.
Granted if I'm wrong on that part please tell me.
Mainly I was just wondering if I made a circuit that was a full adder.

Last edited: Oct 26, 2008
4. ### beenthere Retired Moderator

Apr 20, 2004
15,808
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Think of the truth table for the combination of bits. Arrange the MUX inputs so the output is in agreement with the addition of X + Y.

5. ### Jackal Thread Starter New Member

Oct 26, 2008
4
0
Well...
This is what I'm getting.
Lets say that X = 0, Y = 0, Cin = 1
We would get Input 1 and Input 9.
They are both assigned 1's.
With the circuit it has an XOR gate and AND gate.
Since both are 1's, they cannot be added together to make a Sum because the XOR is meant to make the Sum a 0 or 1, not 10. So we would have the carry out which is an AND gate which means it will only carry out with both of the inputs being 1.
Thus we have Sum = 0, Carry out = 1.

Did I miss anything?

6. ### beenthere Retired Moderator

Apr 20, 2004
15,808
295
Arrange the truth table for X and Y as the bits added, and Carry and Sum as the outputs. Perhaps one MUX outputs only the sum and the other the carry. Arrange for X and Y to select inputs such that the outputs agree with the truth table.

7. ### Jackal Thread Starter New Member

Oct 26, 2008
4
0
X Y Ci S Co Now if you implemented the 0's and 1's I previously assigned they would replace the Inputs.
0 0 0 I0 I8
0 0 1 I1 I9
0 1 0 I2 I10
0 1 1 I3 I11
1 0 0 I4 I12
1 0 1 I5 I13
1 1 0 I6 I14
1 1 1 I7 I15

Is this what you were getting at?
So instead of them actually going together, and having my two gates, 1 is instead already the sum and the other is already the carry out, and just depending on what X, Y and Ci will determine this.

Here's a new drawing if what I think you are getting at.

But this would mean that the two MUXes are actually making the full adder... I don't understand that part, if this is true. Could you help me out?

8. ### beenthere Retired Moderator

Apr 20, 2004
15,808
295
I think if you use a different format for the truth table, it will be more illuminating.

X Y Ci S Co
0 0 0 0 0
1 0 0 1 0

Etc. Notice that the sum comes out of one MUX, while the Carry out comes out of the other (why else would you need 2 multiplexers for the function?). Notice that X, Y and Carry in are the select bits. They are common to both MUX's. Each MUX output should be what is predicted by the truth table.