Hey everyone. I've been told to integrate a mod7 up and down counter together. I've tried using multiplexer and it does work but it counts up to 7 then counts back to 0. BUT i only want it to count up to 6. so it would go like 0-6-0.

Please tell me how to modify the multisim circuit and please also guide me along on which wires to connect to which input. I sometimes can't understand by words so a diagram would be great! Thanks!!!

 

As I see it, the only time 7 appears on the 7seg is for some microseconds, from the time 7 is clocked in the Flip Flops, until the reset signal is propagated through the AND gates. This is expected behaviour.

Do you experience something different or it's just like I say it?

 

I can't say it appears for microseconds cos just like the other numbers it remains there for 1 clk pulse. so i think its counting till 7. or maybe its the multisim problem? If i solder and test the circuit do you think that 7 would not be shown?
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I cant tell if it is only appearing for a short while as just like the other numbers, 7 appears for a clock pulse. Is something wrong with the circuit? I need this by tmr evening. Its night time over here. So i appreciate your help.
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OMGOMGOMG! I found out what's wrong! The last JK FF CLR was connected to Vcc. It should also be connected to the Nand Gate output! Thanks for your help! Can't beleive i missed it.
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DAMN! It looked ok when it didn't show 7. Now it does not count down so my modification was wrong. What to do now?

 

I really can't see what could be wrong in your schematic. Could it be a bad connection?

Could you take the trouble to post a plot of the following voltages:
Clock
The Q output of each FF
The final AND gate reset signal.

 

The first picture shows the plot of the clk at the top.
followed by output q of FF1 (left side FF)
then q2
then q3

Second picture shows the clk at the top,
q4 output
nand gate output reset signal

I gtg now. Hope you can solve my problem by tmr.

 

That's not really helpful. I was hoping to see the graphs of the voltages when the count hits 7.

It will also help if you upload the .ms file for me to work with.

On another note, wiring the up/down selector with Q4 won't do anything, because your count goes up to 7, not 8 and thus Q4 will always be 0.

If you really must build this with nothing but FFs and gates, why don't you take a look in the up/down counter found here: http://www.allaboutcircuits.com/vol_4/chpt_11/3.html

The only addition needed is a two output logic function that controls the inputs of an SR latch. You want the following behaviour:
When the count is 0:SR=10
When the count is 6:SR=01
All other cases: SR=00

The output of the latch will control the count direction.

Is that clear?

 

Here's the circuit.

 

Okay, your circuit is by design faulty. Here is why:

Your count starts normally from 0 and goes up.
When Q3 goes from 0 to 1, the AND gates trigger immediately the 3 LSB FFs reset. When that happens, Q3 goes from 1 to 0, Q4 goes from 1 to 0, changing the MUX select pin.
Since the count is reset, the next count will be 000. But because you now take the complement as a count, the complement of 000 is 111 or 7, thus the 7 display.

It is now obvious that the problem is the use of the count complement to display the countdown sequence. If you want to get 0 in your sequence, you will always have 7 in it too.
A slight workaround is to reset your sequence to 1, instead of 0. That will give you a count of 1,2,...,6,6,5,4,...,1,1,2,... etc. But it's not what you exactly want.

If I were you, I would trash that design and go with the one I talked about in my previous post.

 

Thanks for the reply. Can u design the circuit in multisim for me? I've never used SR latch before and this is kind of urgent. I'll understand it after my submission ok? There isn't any limitations on what to use for my project. So SR latch JK and logic gates then. Thank you.

 

I won't design the circuit for you. It would take me at about an hour, and I'd rather devote that time to solve my own university exercises. If someone else wants to do it, I won't stand in their way, though.

Here is a link for the SR latch: http://en.wikipedia.org/wiki/SR_latch#Simple_set-reset_latches
It's not anything more than two NAND or NOR gates paired in a specific way.

Errata: Notice that I have edited post #6. The JK input was changed into SR.

 

Its ok. My friend made this which can count up to and down from any number. Thanks for ur help and all the best for your degree. The 4 switches below are 1 when closed and 0 when open. Left switch MSB. right LSB. Top switch is to reset it to 0

 

Thanks.

That's a good overall build. Cudos to your friend. I hope I helped its design phase in some way. It's a pity it counts down to F, crossing 0, but that's not too big of a deal. It can be fixed easily:

One can AND the inverter signal controlling the JK-FF clock with the output of another gate array, one that will detect the 0000 state, giving out a 0. One such circuit is a 4-input OR gate. (Note that a 4-inptu OR gate doesn't really exist as a single IC. You 'll have to replace it by an equivalent circuit.)

That way you will have two points of count direction change. One by your custom selection switches and one by 0.
As of now. The two points are the custom selection and 1111.

I used your file to modify it and build what I described above. I can't save as an .ms10 file, so I attached an image just in case you can't open an .ms11.

 

Thank you very much Georacer! You've been very helpful