It will also help if you can upload the DDR I/O block diagram you are looking at.Vref here is refered to as the Reference Voltage. Now i'm looking right now at a DDR I/O block, which uses SSTL.
This link goes some way to diagramatically explaining what n9352527 has described.VREF is the reference voltage used at the receiving end of the SSTL as the threshold voltage between logic high and low. Usually, VREF is set at half of VDDQ - VSSQ over external variations such as voltage, process, temperature, etc. It is also highly desirable for VREF to be symmetrical between VOH and VIL. The VTT (termination voltage) also has to very closely match VREF.
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