Hi guys i need help understanding mosfets. Basically, i have the circuit as shown. Its a buck converting with a 555timer (to drive the mosfet) attached. What i dont understand is that what resistance (r77) will i need so that the mosfet wont be always on....actually i dont really understand what the resistance there does...

Thanks in advance cheers.

 

R77 is pulling the output of the inverter up

the MOSFET should be turning on and off at the switching frequency of the inverter.

i assume that te Fs=50kHz is the pulse frequency of the signal controlling the FET gate.

 

That gate drive won't work very well.

To turn an NMOS on you need to apply a Vgs, gate-to-source voltage. You're applying a gate voltage, the source voltage is a node that has a varying voltage.

 

yea, i didnt really get how that circuit was going to work.

 

The scheme would work with a PMOS however... then the pull up resistor might make sense if that logic gate was open-collector which it isn't.

 

why not just use an opamp with +/-15V rails to provide enough voltage to drive the gate?

it really is a confusing looking thing.

i think the idea is that the inverter only has to pull the gate to ground, and since it is common emitter (i think?) it should be able to pull low fairly well.

i still dont think pulling a 7404's output up to 30V is a wise idea.

 

The old fashioned 7404 output high is only 3.5V but the Mosfet gate needs 10V.
Your circuit does not have a supply voltage shown but if it is higher than about 7V then R77 will not turn on the Mosfet properly and will cause the output of the old 7404 to be damaged.

 

to the OPs question about R77's value to ensure the FET turning off, try a high value resistance (10k-100k range) and see if that helps, right now you are pulling a lot of current through that 300Ω resistor which will make it next to impossible for the 7407 to sink all of it when it tries to drive low.

unfortunately, this may not work at all, because when limiting to 5-10 mA for the 7404s sake, you may not have enough bias current to open the gate of the FET.

some quick math and datasheet investigation should tell you if this will work reliably or not.

 

The problem with using an NMOS on the high side is that Vgs must be a large positive voltage and by definition the drain is at a slightly higher voltage than the source.
Since the drain is your power supply, the NMOS gate must be driven above the source.

People do this with bootstrapping (generating a voltage above supply) or isolated gate drivers (referencing gate voltage to the source regardless of what it is).

A ground referenced driver like this just won't cut it for an NMOS.
For a PMOS you just need the gate voltage lower than the source (connected to the supply voltage) which is easily done by a pull down network.

 

The problem with using an NMOS on the high side is that Vgs must be a large positive voltage and by definition the drain is at a slightly higher voltage than the source.
Since the drain is your power supply, the NMOS gate must be driven above the source.

People do this with bootstrapping (generating a voltage above supply) or isolated gate drivers (referencing gate voltage to the source regardless of what it is).

A ground referenced driver like this just won't cut it for an NMOS.
For a PMOS you just need the gate voltage lower than the source (connected to the supply voltage) which is easily done by a pull down network.

i am trying to digest all of that, my level of understanding of FET/BJT devices with PNP/NPN high/low side drivers is not really as thorough as id like.

hopefully some of this is covered in the art of electronics.

thanks for that explanation though.

i didnt notice that in fact, while the source is grounded when the FET is off, when the FET is on it is going to be the voltage output.

so there will be no differential when the FET is conducting and therefore it really just wont work.

sorry, that may have been me "thinking outlloud" in a post.

 

i am trying to digest all of that, my level of understanding of FET/BJT devices with PNP/NPN high/low side drivers is not really as thorough as id like.

hopefully some of this is covered in the art of electronics.

thanks for that explanation though.

i didnt notice that in fact, while the source is grounded when the FET is off, when the FET is on it is going to be the voltage output.

so there will be no differential when the FET is conducting and therefore it really just wont work.

sorry, that may have been me "thinking outlloud" in a post.

You have it slightly backwards.
When the FET is on the source should be the input voltage, it's supposed to be an ideal switch. The inductor holds the voltage difference between input and output, getting charged up.

The thing will still switch but it won't be very good at all. The source voltage is a negative diode drop while the FET is off and then as the FET tries to turn on that voltage will quickly rise as the diode turns off.

If you drive the gate higher than the supply (drain) voltage, then when the source rises to roughly the supply voltage you still have a positive Vgs.

 

Here are some shots from a simulation.

I'm simply driving the gate with a ground referenced voltage source.

The plots are drain, source, gate, and gate-source voltages.
Input voltage is 30V.

When the gate is driven at 10V, the standard "well driven" number (the actual voltage threshold is closer to 3V) we get this:



Nothing good really happens. The transistor cannot turn on fully, because Vd = 30V and Vg = 10V.
For the transistor to be on at all, Vgs > Vth, or Vg > Vs + Vth. Because the transistor does get turned on, you force Vs = 10 - 3 = 7. That gives you Vds = 23V, indicating that it's obviously in the high resistance region.
An NMOS cannot "pull higher than gate minus threshold". That idea is commonly applied in digital circuits.

If we drive it with Vin, 30V, you get this:



Again the source is only pulled up to Vg - Vth, or 27V. You have Vg = Vd or Vds = Vth, which again isn't exactly low resistance. Remember a MOSFET is in the triode (on) region when Vgs > Vds + Vth, or Vg > Vd + Vth

Now I drive it with 40V, which is Vin + 10V:



Notice that now the source gets pulled all the way up to Vin (30V) and the gate source voltage actually becomes 10V.

 

thanks

 

and i graduated cum laude from an ABET accredited EE program.

go education system!

 

That's how it goes I guess. School just doesn't teach everything... it gives you tools and fundamentals so you can move on with your learning.
This simple fact was barely mentioned in my two undergrad power electronics courses and it was mentioned briefly in the transistor level digital electronics course as one of the benefits of CMOS.
You'll always need to piece things together no matter how much you study

 

MOSFETs

 

omg thanks for all the reply...... but er... IM LOST !!so basically, will this circuit work? Any suggestions what i can do to turn on the mosfet?

 

ok let me show u the whole circuit that i have made... together with the 555 timer, and im building on a current mirror that i dont understand how it can vary the duty cycle... basically the main objective is for me to be able to adjust the voltage from the "current mirror circuit" which i have not designed....

 

sorry note that im usign IRFz44 instead of 150..

 

This will not work. TTL is a 5V logic, and a one in TTL is around 3.5V. You need at least 10V on the gate. I suspect you haven't tried all the links people have given you. A MOSFET requires 10V on the gate to turn fully on.

Transistor Drivers

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