Mosfet current ratings

Thread Starter

sdrawkcab

Joined May 14, 2007
4
I've been browsing through some datasheets for power mosfets, and a lot of the high-current ones will have a footnote for the Idmax rating that says "current limited by package." Here's one example:

http://www.vishay.com/docs/71109/71109.pdf

Is it a thermal limit? Would you be able to get the rated current with a proper heatsink? Or is it the current limit of the actual package leads? If it is, would the through-hole packages have a higher limit than the surface mount packages?

And how could you figure out how much the package current limit differs from the published limit?
 

John Luciani

Joined Apr 3, 2007
477
I've been browsing through some datasheets for power mosfets, and a lot of the high-current ones will have a footnote for the Idmax rating that says "current limited by package." Here's one example:

http://www.vishay.com/docs/71109/71109.pdf

Is it a thermal limit? Would you be able to get the rated current with a proper heatsink? Or is it the current limit of the actual package leads? If it is, would the through-hole packages have a higher limit than the surface mount packages?

And how could you figure out how much the package current limit differs from the published limit?
The current is limited by the amount of power that the package can dissipate.
In most applications the current will be limited the Rds(on) of the FET which increases with temperature. There should be a graph in the datasheet that plots Rds(on) versus
temperature. Determine the temperature rise of the FET and you can determine
the Rds(on).

Getting the rated current almost always requires proper heatsinking. With the
SMD packages you need to provide a large copper area under the drain pad
(which can consume a fair amount of PCB area). For a through-hole device
you can get the heatsink off of your board. The best choice depends on your
system.

You can parallel the drains of multiple FETs to increase the current. Depending
on your application you may need a control loop for each FET.

(* jcl *)
 
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