Hello,
I looked at some other threadsand didn't find anything that could help me. So I have an assignment to make a 4 bit sequential counter that counts down one step and starts from 12. (B,A,9,8,7,6,5,4,3,2,1,0,B,A...etc)
I'm using JK flip-flops as T trigers and connect them from \(\bar{Q}\). My enable has to vary between "1" and "0" together with the clock but twice as slow. Meaning it cant have a constant value of 1. It's to show that Enable has some affect to the counting process.
To have the counter start from 12 I take the positive feedback from Q3(the oldest) and Q2 using a "NAND" gate and connect it through another "AND" gate to JK of the third triger, the second signal to the "AND" gate comes from the "AND" of the second triger. Since if both he Q3 and Q2 have the value of "1" at the same time then Q2 has to have a next value "0", thus making it impossible for F,E,D and C to appear. But what it does is it even makes 7,6,5 and 4 to disapear. since they all have the value of "1" in the third rank of their binary (don't know if it's the right word, hope you understand) then the fault lies there somewhere, only I can't put a finger on where exactly.
I had a working counter that had maybe too many gates and the 3,2,1 and 0 took twe as much time to count as the rest,but only when enable was twice as slow than the clock. As it must be for me. But my teacher wasn't satisfied with that and so now i need to make another one but am stuck wit a counter that should work in theory, atleast i think it should.
Picture is worth more then a 1000 words, so i'll upload the one i'm stuck with and the one that "works".
Stuck with that:
That's the one that works:
Thanks in advance, hope it wasn't too much of a heavy reading
Juho
I looked at some other threadsand didn't find anything that could help me. So I have an assignment to make a 4 bit sequential counter that counts down one step and starts from 12. (B,A,9,8,7,6,5,4,3,2,1,0,B,A...etc)
I'm using JK flip-flops as T trigers and connect them from \(\bar{Q}\). My enable has to vary between "1" and "0" together with the clock but twice as slow. Meaning it cant have a constant value of 1. It's to show that Enable has some affect to the counting process.
To have the counter start from 12 I take the positive feedback from Q3(the oldest) and Q2 using a "NAND" gate and connect it through another "AND" gate to JK of the third triger, the second signal to the "AND" gate comes from the "AND" of the second triger. Since if both he Q3 and Q2 have the value of "1" at the same time then Q2 has to have a next value "0", thus making it impossible for F,E,D and C to appear. But what it does is it even makes 7,6,5 and 4 to disapear. since they all have the value of "1" in the third rank of their binary (don't know if it's the right word, hope you understand) then the fault lies there somewhere, only I can't put a finger on where exactly.
I had a working counter that had maybe too many gates and the 3,2,1 and 0 took twe as much time to count as the rest,but only when enable was twice as slow than the clock. As it must be for me. But my teacher wasn't satisfied with that and so now i need to make another one but am stuck wit a counter that should work in theory, atleast i think it should.
Picture is worth more then a 1000 words, so i'll upload the one i'm stuck with and the one that "works".
Stuck with that:
That's the one that works:
Thanks in advance, hope it wasn't too much of a heavy reading
Juho