microcontrollers expansion capability multiplex

Thread Starter


Joined Apr 29, 2011
Hey guys :)

I dont think I fully understand this question. Am I right? or am I missing the point?

What is the reason most microcontrollers that have expansion capability multiplex part of the address bus with the data bus on a common I/O port?

From what I have been reading,
A multiplexed expanded bus, uses a common data and address bus because there is not enough I/O pins to separate the busses... I dont even fully understand this:confused:

Can anyone explain this to me?

thanks guys :)


Joined Aug 15, 2007
In both cases, assuming a 16-bit address bus, and an 8-bit data bus, the address bus uses 16 pins. In the NON-multiplexed bus, the Data bus takes an additional 8 bits, for a total of 24 bits. In the multiplexed bus, the Data bus takes NO additional pins (or 1 pin if you want to consider the Address Latch Enable) for a total of 16 or 17 pins.


Thread Starter


Joined Apr 29, 2011
thanks alot Rich.
I'm sorry, I'm still not quite getting it :(.
Could you maybe explain the advantages? (If you can, in simple terms)

thanks a lot for your help


Joined Jul 27, 2011
This image gives a good sense of the basic idea:

For this microcontroller (left), Port PA7:0 is an 8-bit port that functions as both the low-byte of the 16-bit external address and an 8-bit data port.

A generalized write process might be:

1.) The full 16-bit address is placed on ports PA7:0 and PC7:0

2.) The Address Latch Enable (ALE) pin goes high (PG2 in this picture.) and the external latch (the small chip in the middle on this image) latches (saves) the low byte of the address.

4.) Port PA7:0 on the microcontroller switches from the address low-byte value to the data value.

5.) Write Enable pin goes high (PG0) signalling the external ram to "store" the data on D7:0 at the address A15:8-A7:0

The latch is there to store the low byte of the address so that when the microcontroller switches PA7:0 from the low-byte of the address to the data value, the RAM still has access to the full address. This latch can be a separate chip or internal to the RAM itself.

As Rich mentioned, if the low-byte of the address was not multiplexed onto port PA7:0, you'd need 16 pins on the microcontroller for the address, and another 8 pins for the data. Here, the 8 data pins are shared with 8 of the address pins.