Hi friends,

Could somebody provide me sample designs or projects of Spartan-6 DDR3 Memory controller interface with MIG (Memory Interface Generator) ?

The reference design from Xilinx is confusing and complicated..Please Help me!

Thank you!
Sam

 

Hey Sam,

I had a project where i wanted to use a DDR2 controller on a spartan 3e. Never got around to testing it all though.

But from what i gathered, you probably want to try and use the CoreGen program that comes with ISE. You basically give it your system parameters and it spits out the code for the controller/setup. There's some documentation on it... i can try and dig it up if i can't find it.

You might want to try the xilinx forums... they're very helpful and xilinx tech support regularly visit to help.

Good luck!

 

Hi Guitarguy,

Thanks for the reply. The reference design by xilinx for spartan-6 fpga has no documentation. I am confused with which components to be used within the design.

I want to implement a simple write user logic. Do u have any idea how that works?

Thank you!
Sam.

 

No problemo.

Check out chapter 7 of Xilinx Tech Doc UG086 (Memory Interface Solutions User Guide). It has tons of info, including timing diagrams for the read/write logic. I dont't really remember exactly how the controller works. I believe it will be a non-trivial matter to learn the system, though.

What reference design are you using?

 

Hi Guitarguy,

I meant the Traffic Generator reference design.

Refer: UG416 (v1.31) Page no:36 - MIG EXAMPLE DESIGN WITH TRAFFICE GENERATOR.

Have u worked with MIG already?

Sam.

 

Check out chapter 7 of Xilinx Tech Doc UG086 (Memory Interface Solutions User Guide).

The new MCB controller in spartan-6 is advanced and the design differs from that of spartan-3 devices..