Memory Bus Termination

Discussion in 'General Electronics Chat' started by Skeebopstop, Jun 19, 2009.

  1. Skeebopstop

    Thread Starter Active Member

    Jan 9, 2009
    Hi All,

    I am currently working with a parallel memory bus operating at 10nS, with 3nS rise times.

    General termination practices tell me that I can route up to 30cm and generally be ok (Rise time < 2 * propogation delay).

    My main question is, for really high speed parallel buses (perhaps they don't exist because of this problem), how would you terminate it properly? Lets say a 1GHz parallel memory bus which requires tracking of up to 30cm. Do people really put in 16 termination resistors at ~ 80R (PCB line impedance)?