Design a circuit that stores the 5-bit result of the last addition operation of a 4-bit full adder to a 8 words by 4-bit memory.

1- Store the MSB of the 5-bit result to the bit 0 in the address 000. Ensure that all other bits are set to 0.

2- Store the other 4-bits of the output in the address 001 of the memory.

3- Use a given clock signal to execute the above steps and write to memory.

I can see how the full adder arrangement would be in parallel with the carry out running into the next full adders carry in but I'm confused about how to design the memory portion of the circuit.

How can I ensure that MSB of the result is in the bit 0 of the address 000 as well as assigning the other 4 bits to the address 001? Is this going to be happening at the same time? How can I do this?

Also, what is the easiest way to ensure that the rest of the data bits in the address 000 are 0?

Thanks again!

 

Must you choose the storing address every time, or you will strore the results circularly in the memory?

In any way, it is important to specify what kind of memory it will be used. Must you build the memory too?