Hi,

I'm doing a project in which I need to monitor a signal, let's say monitored_signal and if it is active for more than 5.3s enable another signal, let's say enabled, if monitored_signal is active for less than 5.3s than enable is inactive.
Any idea about how I can do this without CPLD/FPGA?

Thanks.

 

A monostable IC and a bit of logic is one way.

Attached is a really crude logic circuit that will do it. CR time constant needs to be 5.3s. If using CMOS logic then R can be quite a high value, say 1MΩ

It's crude, because the performance of the circuit depends on the signal source impedance (and voltage). Also, the capacitor takes time to discharge through the diode, therefore the time-constant depends on how long it was since the last input pulse.

 

1. How does the logic level affect the choice of R and C.

2. I'm a bit confused shouldn't the amount of time be determined by the RC constant, like this: if I want the time to be equal to 5s then the RC constant = 5s. And by picking R I determine C or viceversa. But my calculations are contradicted by some simulations I ran. Where am I going wrong?

 

You are correct. The time constant is CR. So 1MΩ and 5μF gives 5s. But this is the time to charge from zero to about 63% of the supply voltage. The threshold of the gate will probably be different from this and the capacitor may not be charging from zero.

This are some of the limitations of this simple circuit.

 

Hi,

I'm doing a project in which I need to monitor a signal, let's say monitored_signal and if it is active for more than 5.3s enable another signal, let's say enabled, if monitored_signal is active for less than 5.3s than enable is inactive.
Any idea about how I can do this without CPLD/FPGA?

Thanks.

How accurate does the >5.3 detection have to be? How often does the input go high? How often does the input last longer than 5.3 seconds. How long does the enabled output signal have to remain high (?) after the input has been high for...say...5.30001 seconds then goes low.

Ken