Max Propagation Delay temp or path?

Thread Starter

Tera-Scale

Joined Jan 1, 2011
164
I am asked to find the maximum propagation delay of a subtractor i designed by referring to the data sheet of each ttl IC. Do I have to take it in terms of temperature effecting the the operation (from datasheet) or is it a matter of the longest path (number of gates to encounter) for a logic state to be established at the output?

Brandon
 

Georacer

Joined Nov 25, 2009
5,182
When I am asked to do such calculations, they want me to use the longest logical path and the typical IC delay, the temperature effect not being taken into account.
 

Thread Starter

Tera-Scale

Joined Jan 1, 2011
164
I checked with my lecturer and it was exactly as you said - the temperature shouldn't come in here and it is important that if I used the typical or the worst case scenario .. it should be noted down.
 
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