I'm currently making a (very low power) 60kHz transmitter. Because 60kHz crystals are not very widely available, I am dividing a 6MHz square wave by 100 in order to obtain a 60kHz signal.

When performing this division however, the output of the divider does not have a mark/space ratio of 50/50. The output is high for 1.67e-7 S (period of 6MHz signal) and low for the rest of the 60kHz period.

Does this matter for a transmitter? Would feeding this signal to a resonant LC circuit transmit less efficiently than a signal with a 50/50 mark/space ratio?

Many thanks.

 

I'm currently making a (very low power) 60kHz transmitter. Because 60kHz crystals are not very widely available, I am dividing a 6MHz square wave by 100 in order to obtain a 60kHz signal.

When performing this division however, the output of the divider does not have a mark/space ratio of 50/50. The output is high for 1.67e-7 S (period of 6MHz signal) and low for the rest of the 60kHz period.

Does this matter for a transmitter? Would feeding this signal to a resonant LC circuit transmit less efficiently than a signal with a 50/50 mark/space ratio?

Many thanks.

Short answer...yes. Driving a tank circuit with a square wave will have the most energy with a symmetrical wave. Also, the harmonics are easier to filter with a symmetrical wave.

I'm not sure why your divider isn't giving you symmetrical waves, however...especially at such a low freqency. You might try applying a slight DC bias to the input of whichever divider is misbehaving and see if you can twiddle the duty cycle. YOu might have a chip with a little hysteresis. Be sure you don't have any floating inputs on any chips either.

eric

 

I am not familiar with transmitters but I know that you as you reduce the period of a pulse you need higher frequencies to keep it undistorted and thus you need greater bandwidth.

 

Logic dividers/counters don't give symmetrical waves unfortunately. They are only high for the time period of the input clock signal, and then remain low until the counter comes round again (that's a horrendous explanation, hope you understand!).

One thing I just thought that I could do is double the frequency of the divider (so 120kHz), and feed that into a T-flip flop. That will give mea 60kHz square wave.

 

I am not familiar with transmitters but I know that you as you reduce the period of a pulse you need higher frequencies to keep it undistorted and thus you need greater bandwidth.

Mik3... This is actually a pretty fascinating topic. As you know, a square wave gives you the fundamental, plus all the ODD harmonics. (Pretty simple Fourier analysis at this point) However, when you have UNSYMMETRICAL square waves, you start getting additive and subtractive components....products of your fundamental square wave frequency PLUS what you would have if your shortened pulses WERE symmetrical! For example, if you have a 1KHz square wave with a 25% duty cycle, you have not odd harmonics of 1KHz, but you have odd harmonics of 4 KHZ, PLUS all the sums and differences possible!

Eric

 

You can get a symmetrical bi-quinary divide by 10 output by using a 74x90 counter.

Feed the input signal to the B clock/input B/CP1. The A clock/input A/CP0 is connected to the Q3/Qd output. The symmetrical output is taken from Q0/Qa.

If you wired two 74x90 counters that way in series to your 6MHz clock, you'd have a perfectly symetrical 60kHz output.

You'll need a low-pass filter to get a decent sinewave output. I whipped up a 7-pole Butterworth LC filter for you using Elsie. Schematic and plots attached. The harmonic at 120kHz will be 22dB down. A Chebychev design would be more appropriate (closer to a "brick wall" response) but you might have a time trying to tune it.
But, I'll attach it anyway.

60kHz is the frequency for the WWVB NIST Time Signal.
http://tf.nist.gov/stations/wwvb.htm
If you happen to interfere with that signal, expect the FCC to break down your door, sieze your equipment, and toss you in the hoosegow. The FCC does not give warnings, nor do they have a "sense of humor".

 

Logic dividers/counters don't give symmetrical waves unfortunately. They are only high for the time period of the input clock signal, and then remain low until the counter comes round again (that's a horrendous explanation, hope you understand!).

One thing I just thought that I could do is double the frequency of the divider (so 120kHz), and feed that into a T-flip flop. That will give mea 60kHz square wave.

If you drive each stage with a DIFFERENTIATED pulse, rather than just relying on the leading edge of the square wave, you SHOULD have a perfectly symmetrical waveform.


eric

 

Thanks very much for that SgtWookie - much appreciated, I'll have a good look at it at home.

For the record, I'm in the UK, but the same applies as we have an MSF time signal here on 60kHz. My transmitter will only transmit a matter of feet so shouldn't be an issue that would result in ofcom tracking me down!

KL7AJ: What do you mean by a differentiated pulse?

 

Thanks very much for that SgtWookie - much appreciated, I'll have a good look at it at home.

For the record, I'm in the UK, but the same applies as we have an MSF time signal here on 60kHz. My transmitter will only transmit a matter of feet so shouldn't be an issue that would result in ofcom tracking me down!

KL7AJ: What do you mean by a differentiated pulse?

Basically a pulse of infinitesimal length. This is what you should always use for a clock pulse. You can get one by taking a square wave and running it through a high-pass RC network with a VERY short time constant.


Eric

 

Can't say I agree entirely with Eric. Extremely short pulses require very high bandwidth signal paths; even a 50% duty cycle square wave will become distorted quite quickly due to parasitic RLC's in a circuit.

But anyway, I've attached a relatively simple schematic of three RC differentiator circuits along with input & output waveforms. Notice that waveforms C and D wind up having peak voltages nearly double that of the input 5v square waves.

 

Can't say I agree entirely with Eric. Extremely short pulses require very high bandwidth signal paths; even a 50% duty cycle square wave will become distorted quite quickly due to parasitic RLC's in a circuit.

But anyway, I've attached a relatively simple schematic of three RC differentiator circuits along with input & output waveforms. Notice that waveforms C and D wind up having peak voltages nearly double that of the input 5v square waves.

Hi Sarge:

You're definitely correct that you don't want to drive the R.F. amplfier with a differentiated pulse! I just meant the intermediate stages of the divider, where bandwidth and distortion are irrelevant....differentiated pulses get rid of the PW ambiguity. The pulses between every stage should be evenly spaced....if they aren't something's definitely broken!

eric

 

You can get a symmetrical bi-quinary divide by 10 output by using a 74x90 counter.

I've simulated this and that does appear to work very effectively, so thanks very much!

As it happens, you can use a 74x390, which is a dual version of the 74x90, available in a 16-pin package. Available from Farnell in the UK for £0.25.

http://tinyurl.com/68sr33