Discussion in 'Programmer's Corner' started by Mathematics!, Mar 13, 2012.

  1. Mathematics!

    Thread Starter Senior Member

    Jul 21, 2008
    I am learning makefiles and I am wondering about a few things

    I have been looking at the example

    Code ( (Unknown Language)):
    1. objects = main.o kbd.o command.o display.o \
    2.           insert.o search.o files.o utils.o
    4. edit : $(objects)
    5.         cc -o edit $(objects)
    6. main.o : main.c defs.h
    7.         cc -c main.c
    8. kbd.o : kbd.c defs.h command.h
    9.         cc -c kbd.c
    10. command.o : command.c defs.h command.h
    11.         cc -c command.c
    12. display.o : display.c defs.h buffer.h
    13.         cc -c display.c
    14. insert.o : insert.c defs.h buffer.h
    15.         cc -c insert.c
    16. search.o : search.c defs.h buffer.h
    17.         cc -c search.c
    18. files.o : files.c defs.h buffer.h command.h
    19.         cc -c files.c
    20. utils.o : utils.c defs.h
    21.         cc -c utils.c
    22. clean :
    23.         rm edit $(objects)

    which can be simplified to
    Code ( (Unknown Language)):
    1. objects = main.o kbd.o command.o display.o \
    2.           insert.o search.o files.o utils.o
    4. edit : $(objects)
    5.         cc -o edit $(objects)
    7. main.o : defs.h
    8. kbd.o : defs.h command.h
    9. command.o : defs.h command.h
    10. display.o : defs.h buffer.h
    11. insert.o : defs.h buffer.h
    12. search.o : defs.h buffer.h
    13. files.o : defs.h buffer.h command.h
    14. utils.o : defs.h
    16. .PHONY : clean
    17. clean :
    18.         -rm edit $(objects)
    Because of some implicit rule

    But I am going to have tons of .c files in this directory that I am making
    So it would take for ever to write a line out for each .o files as a target with specific dependencies like the above 2 examples do. Even if the implicit rule allows me to leave off the cc -c condition lines

    I thought of this but won't this below simple version recompile all the .c files if any of the .o files have changed. For get for the moment about the .h files

    Code ( (Unknown Language)):
    2. #would this work?
    3. SRCS = start32.c kmain.c
    4. OBJS = $(SRCS:.c=.o )
    6. $(OBJS) : $(SRCS)

    Code ( (Unknown Language)):
    1. $(OBJS) : $(SRCS)
    2. is equivalent to
    3. start32.o kmain.o : start32.c kmain.c
    4.             cc -c start32.c kmain.c
    6. I believe CORRECT ME IF I AM WRONG
    7. so I would think that everytime start32.c change or kmain.c changed it would recompile both when what I want to do is just have start32.c being recompiled when start32.c is modified and kmain being compiled only when kmain.c changes NOT BOTH.
    9. And I don't want to specify each one by its target:dependencies since I am going to have a ton of c files in this directory... so the 2 first makefile examples are not an option.
    Is it even possible or must you manual tell each .o file which .c files it depends on or should recompile.
    Now that I can just add to the SRCS variable in the makefile and OBJS will contain what sources has in it replaced with a .o extension for .c
    Will I still have to have a target : dependency for each object file defeating the whole purpose of me just wanting to compile and newly add or changed files with the minimum dependencies. ( AND ALSO DEFEATING THE PURPOSE OF THE SRCS and OBJS variables )
    Like if I add whatever.c to the SRCS var and then issue make I just want it to compile whatever.c not all the other .c files.
    Obviously you would still have to do the linking target process with all of them again if one .o file was changed but that is obvious.
    Last edited: Mar 13, 2012
  2. MrChips


    Oct 2, 2009
    Why are you doing this? Usually you let the compiler and linker take care of all of this automatically for you.