LTSpice NAND + RS-FlipFlop construction Problem, HELP

Thread Starter


Joined Jun 1, 2012
Hi Guys,
i have a Problem with my NAND-Gate in LTSpice, so i couldn't build a working RS-Flipflip from it yes.

Following instructions were given:
Vdd = 5V ; In1 Pulse(0 5 0 10u 10u 0.5m 1m); In2 Pulse(0 5 0 10u 10u 1.5m 3m)
Pmos w= 40µm l= 15µm
Nmos w= 15µm l= 15µm
Cl = 470nF

Then we had to simulate .tran 0 5m 0 1u startup
And once the DC-Sweep-Simulation

From the Simulation-Pics we had to get tp-low-high and tp-high-low

I dont know whats wrong in the construction... but the simulation doesn't look right because you cant get the tp-low-high and tp-high-low out of it.

Look at the pictures