LTSpice Model: Microchip MCP6V11

Thread Starter

Ziin13

Joined Mar 4, 2013
10
I have spent hours trying to figure out why my MCP6V11 model doesn't work. I keep getting this error: "Analysis: Time step too small; initial timepoint: trouble with node u1:15".

It appears that a lot of people have a similar problem with the Microchip SPICE model, but I haven't found any solid solution for it.
Please let me know if you have any recommendations?

1634072727799.png

Below is the MCP6V11_F.txt model that I downloaded directly from Microchip, then renamed it MCP6V11.sub:

.SUBCKT MCP6V11 1 2 3 4 5
* | | | | |
* | | | | Output
* | | | Negative Supply
* | | Positive Supply
* | Inverting Input
* Non-inverting Input
********************************************************************************
* Software License Agreement *
* *
* The software supplied herewith by Microchip Technology Incorporated (the *
* 'Company') is intended and supplied to you, the Company's customer, for use *
* soley and exclusively on Microchip products. *
* *
* The software is owned by the Company and/or its supplier, and is protected *
* under applicable copyright laws. All rights are reserved. Any use in *
* violation of the foregoing restrictions may subject the user to criminal *
* sanctions under applicable laws, as well as to civil liability for the *
* breach of the terms and conditions of this license. *
* *
* THIS SOFTWARE IS PROVIDED IN AN 'AS IS' CONDITION. NO WARRANTIES, WHETHER *
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED *
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO *
* THIS SOFTWARE. THE COMPANY SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR *
* SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. *
********************************************************************************
*
* The following op-amps are covered by this model:
* MCP6V11/1U/2/4
*
* Date of model creation: 9-6-2019_8:38:50_PM
* Level of Model Creator: 6V11_01S / 08-08-19
*
* Revision History:
* REV A: 17-May-12, Initial Input / REV B: 09-Jul-12, Added MCP6V11U
* REV C: 07-JuL-17, Updated Model Creator 6.14S
* REV D: 24-JuL-17, Updated Rout, Vos, and Vos Drift
* REV E: 08-Aug-19, Updated Output Impedance, Slew Rate plus characterization
* REV F: 06-Sep-19, Removed buffer in Gain/Phase test ckt, adjusted response to match original bode plot. Updated 1/f noise.
*
* Recommendations:
* Use PSPICE (or SPICE 2G6; other simulators may require translation)
* For a quick, effective design, use a combination of: data sheet
* specs, bench testing, and simulations with this macromodel
* For high impedance circuits, set GMIN=100F in the .OPTIONS statement
*
* Supported:
* Typical performance for temperature range (-40 to 125) degrees Celsius
* DC, AC, Transient, and Noise analyses.
* Most specs, including: offsets, DC PSRR, DC CMRR, input impedance,
* open loop gain, voltage ranges, supply current, ... , etc.
* Temperature effects for Ibias, Iquiescent, Iout short circuit
* current, Vsat on both rails, Slew Rate vs. Temp and P.S.
*
* Not Supported:
* Some Variation in specs vs. Power Supply Voltage
* Vos distribution, Ib distribution for Monte Carlo
* Distortion (detailed non-linear behavior)
* Some Temperature analysis
* Process variation
* Behavior outside normal operating region
*
* Known Discrepancies in Model vs. Datasheet:
*
*
*
* Input Stage
*
V10 3 10 -400M
R10 10 11 69.0K
R11 10 12 69.0K
G10 10 11 10 11 1.44M
G11 10 12 10 12 1.44M
C11 11 12 76.8P
C12 1 0 6.00P
E12 71 14 VALUE { (646N) + V(20) * 17.4 + V(21) * 17.4 + V(22) * 17.4 + V(23) * 17.4 }

* Generate Input Bias 1 and 2 and Input Offset
EG12 VIBIAS 0 62 0 1
EG13 VIBIOS 0 63 0 1

* Calculate IB1 and IB2 based on IOS
EIB1 VIB1 0 VALUE { (V(VIBIAS)+V(VIBIOS)) /2 }
EIB2 VIB2 0 VALUE { (V(VIBIAS)-V(VIBIOS)) /2 }

* Convert Voltage to Current on Pins 1 and 2
GIB1 1 0 VIB1 0 1u
GIB2 2 0 VIB2 0 1u

M12 11 14 15 15 NMI
M14 12 2 15 15 NMI
C14 2 0 6.00P
I15 15 4 500U
V16 16 4 -150M
GD16 16 1 TABLE { V(16,1) } ((-100,-100E-15)(0,0)(1m,1u)(2m,1m))
V13 3 13 -200M
GD13 2 13 TABLE { V(2,13) } ((-100,-100E-15)(0,0)(1m,1u)(2m,1m))
R71 1 0 10.0E12
R72 2 0 10.0E12
R73 1 2 10.0E12
*C13 1 2 3.00P
*
* Noise
*
I20 21 20 423U
D20 20 0 DN1
D21 0 21 DN1
I22 22 23 1N
R22 22 0 1k
R23 0 23 1k
*
* Open Loop Gain, Slew Rate
*
G30 0 30 12 11 1
R30 30 0 1.00K
G31 0 31 3 4 5.69
I31 0 31 DC 33.2
R31 31 0 1
E_VDDMAX VDE 0 3 4 1
V_VDD1 31VDD1 0 1.6
V_VDD2 31VDD2 0 5.5
G_ABMII2 0 31B VALUE { V(31)*(LIMIT(((V(31VDD1)-V(VDE))/(V(31VDD1)-V(31VDD2))), 0, 1))}
R_R3 31A 0 1 TC=3.39M, -15.3U
G_ABMII1 0 31A VALUE { V(31)*(LIMIT(((V(VDE)-V(31VDD2))/(V(31VDD1)-V(31VDD2))), 0, 1))}
G_G6 30 31C TABLE { V(30, 31C) } ((-100,-1n)(0,0)(1m,0.1)(101m,190.1))
E_ABM1 31C 0 VALUE { (V(31A) + V(31B)) }
R_R8 31B 0 1 TC=3.15M, -21.4U
G32 32 0 3 4 11.3
I32 32 0 DC 39.6
R32 32 0 1
G_ABMII22 32B 0 VALUE { V(32)*(LIMIT(((V(31VDD1)-V(VDE))/(V(31VDD1)-V(31VDD2))), 0, 1))}
R_R23 32A 0 1 TC=2.98M, -14.0U
G_ABMII21 32A 0 VALUE { V(32)*(LIMIT(((V(VDE)-V(31VDD2))/(V(31VDD1)-V(31VDD2))), 0, 1))}
G_G26 32C 30 TABLE { V(30, 32C) } ((-101m,190.1)(-1m,0.1)(0,0)(100,-1n))
E_ABM21 0 32C VALUE { (V(32A) + V(32B)) }
R_R28 32B 0 1 TC=2.33M, -15.4U
G6 0 33 30 0 1m
R6 33 0 1K
*
* 1st Order Pole
*
G34 0 34 33 0 6.31
R34 34 0 1K
C34 34 0 10.6M
*
* 2nd Order Pole
*
G37 0 37 34 0 1m
R37 37 0 1K
C37 37 0 318P
*
* 3rd Order Pole
*
G377A 0 377A 37 0 1m
R377A 377A 0 1K
C377A 377A 0 795N
*
* 1st Order Zero
*
G38 0 38 377A 0 1m
GR38 39 0 39 0 1m
RR38 39 0 100G
L38 38 39 7.95M
E38 35 0 38 0 1
*
* Output Stage
*
R80 50 0 100MEG
G50 0 50 57 96 2
R58 57 96 0.50
R57 57 57A 10k
LR14 57 57A 79.6M
RR14 57A 0 100
* PSRR / CMRR
G57 0 57 VALUE { V(35) * 10.0M + V(118) + V(127) + V(137) }
*
*
* PSRR Plus Gain and GBWP Pole Neutralization and Wave Shaping
*
* G30 THE DC GAIN FOR +PSRR
G110 0 110 3 0 11.2U
* ADD POLE TO NEUTRALIZE GBWP ZERO
R110 110 0 1G
GR110 110 0 110 0 1M
C110 110 0 10.6M
*
*
* PSRR Plus Pole
*
G111 0 111 110 0 1
L111 111 112 17.6
R112 112 0 1G
GR112 112 0 112 0 1
*
* PSRR Plus Zero
*
G114 0 114 111 0 1
R114 114 0 1G
C114 114 0 795U
GR114 114 0 114 0 1
*
* PSRR Plus 2nd Pole
*
G115 0 115 114 0 1
L115 115 116 159P
R116 116 0 1G
GR116 116 0 116 0 1
*
* PSRR Plus 2nd Zero
*
G117 0 117 115 0 1
R117 117 0 1G
C117 117 0 159P
GR117 117 0 117 0 1
*
* PSRR Plus 3rd Pole
*
G118 0 118 117 0 1
L118 118 119 159P
R119 119 0 1G
GR119 119 0 119 0 1
*
* PSRR Minus Gain and GBWP Pole Neutralization and Wave Shaping
*
* G40 THE DC GAIN FOR -PSRR
G120 0 120 4 0 11.2U
* ADD POLE TO NEUTRALIZE GBWP ZERO
R120 120 0 1G
GR120 120 0 120 0 1M
C120 120 0 10.6M
*
*
* PSRR Minus Pole
*
G121 0 121 120 0 1
L121 121 122 17.6
R122 122 0 1G
GR122 122 0 122 0 1
*
* PSRR Minus Zero
*
G124 0 124 121 0 1
R124 124 0 1G
C124 124 0 795U
GR124 124 0 124 0 1
*
* PSRR Minus 2nd Pole
*
G125 0 125 124 0 1
L125 125 126 159P
R126 126 0 1G
GR126 126 0 126 0 1
*
* PSRR Minus 2nd Zero
*
G1217 0 127 125 0 1
R127 127 0 1G
C127 127 0 159P
GR127 127 0 127 0 1
*
* CMRR Gain and GBWP Pole Neutralization and Wave Shaping
*
* G50 THE DC GAIN FOR CMRR
G130 0 130 VALUE { ( V(15) ) * 10.0U}
* Add Zero To Neutralize GBWP Pole
R130 130 0 1G
GR130 130 0 130 0 1m
C130 130 0 15.0M
*
*
* CMRR Pole
*
G131 0 131 130 0 1
L131 131 132 2.65
R132 132 0 1G
GR132 132 0 132 0 1
*
* CMRR Zero
*
G133 0 133 131 0 1
R133 133 0 1G
C133 133 0 795U
GR133 133 0 133 0 1
*
* CMRR 2nd Pole
*
G134 0 134 133 0 1
L134 134 135 7.96U
R135 135 0 1G
GR135 135 0 135 0 1
*
* CMRR 2nd Zero
*
G137 0 137 134 0 1
R137 137 0 1G
C137 137 0 39.7U
GR137 137 0 137 0 1
*
GD55 55 57 TABLE { V(55,57) } ((-0.2m,-400)(-0.1m,-1m)(0,0)(10,1n))
GD56 57 56 TABLE { V(57,56) } ((-0.2m,-400)(-0.1m,-1m)(0,0)(10,1n))
C555 55 57 1P
C557 57 56 1P
E55 55 0 VALUE { 600U + V(3) * 1 + V(51) * -56.0M }
E56 56 0 VALUE { -577U + V(4) * 1 + V(52) * -45.7M }
R51 51 0 1k
R52 52 0 1k
GD51 50 51 TABLE { V(50,51) } ((-10,-1n)(0,0)(1m,1m)(2m,1))
GD52 50 52 TABLE { V(50,52) } ((-2m,-1)(-1m,-1m)(0,0)(10,1n))
G53 3 0 VALUE { -500U + V(51) * 1M }
G54 0 4 VALUE { -500U + V(52) * -1M }
*
* Current Limit
*
G99 96 5 99 0 1
R98 0 98 1 TC=-7.05M,19.9U
G97 0 98 TABLE { V(96,5) } ((-11.0,-8.00M)(-1.00M,-7.92M)(0,0)(1.00M,7.92M)(11.0,8.00M))
E97 99 0 VALUE { V(98) * LIMIT((( V(3) - V(4) ) * 357M + 107M), 0.00, 1E6 ) * LIMIT((( V(3) - V(4) ) * 400M + 0.00), 0, 1) }
D98 4 5 DESD
D99 5 3 DESD
*
* Temperature / Voltage Sensitive IQuiscent
*
R61 0 61 1 TC=2.70M,-7.11U
G61 3 4 61 0 1
G60 0 61 TABLE { V(3, 4) } ((0, 0)(500M,61.0N)(1.5,5.6U)(2.5,5.8U)(3.5,6.00U)(4.5,6.1U)(5.5,6.2U))
*
* Temperature Sensitive offset voltage
*
I73 0 70 DC 1
R74 0 70 1 TC=5.00N
E75 1 71 VALUE {V(70)-1}
*
* Temp Sensistive IBias
*
I62 0 62 DC 1uA
R62 622 62 REXP 4.73598
R622 0 622 REXP_2 83.17738U
*
* Temp Sensistive Offset IBias
*
I63 0 63 DC 1uA
R63 633 63 REXP2 50.54068
R633 0 633 REXP_4 150.72187M
*
*
G57X 0 57X VALUE { V(35) * 10.0M + V(118) + V(127) + V(137) }
R57X 57X 57AX 10k
LR14X 57X 57AX 79.6M
RR14X 57AX 0 100
G35X 33 0 TABLE { V(57X,3) } ((-1,-1p)(0,0)(500M,1n)(1.00,1))
G36X 33 0 TABLE { V(57X,4) } ((-1.00,-1)(-500M,-1n)(0,0)(1,1p))
*
* Models
.MODEL NMI NMOS(L=2.00U W=42.0U KP=200U LEVEL=1 )
.MODEL DESD D N=1 IS=1.00E-15
.MODEL DN1 D IS=1P KF=14.6E-20 AF=1.3
.MODEL REXP RES TCE= 1.3865
.MODEL REXP_2 RES TCE= 17.84466
.MODEL REXP2 RES TCE= 540.46288M
.MODEL REXP_4 RES TCE= 7.82344
.ENDS MCP6V11
 

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Papabravo

Joined Feb 24, 2006
17,029
The model has problems.

You would not normally connect the positive supply pin through a resistor. The error message is telling you that NODE 15, in the the sub circuit file has a problem. In particular it is not possible to compute a DC operating point for this particular device. NODE 15 is associated with a current source (I15) in the input section of the model. Simplifying the circuit by removing all the resistors, moves the problem to NODE 30. that lead me to believe that there is more than one problem so that pretty much eliminates any chance of my being able to help you.

I have a similar opamp (TSV911) that works just fine as a single supply voltage follower.
 

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Thread Starter

Ziin13

Joined Mar 4, 2013
10
@Papabravo

Thanks for the rapid response. I did try to delete all the resistors and still got the same error you mentioned.

I have been using the LTC2066 as an alternative model, but really want to solve the issue on the MCP6V11. It bugs me so much that I start disliking microchip components.

1634078342187.png
 

Papabravo

Joined Feb 24, 2006
17,029
Hi Bordodynov

Can you please provide some info about your capture? It doesn't look like LTSpice Software to me.

Thanks,
It most certainly is LTspice, but Alex (Bordodynov) has chosen to alter the default color scheme for both schematics and waveforms.
His fix was to add some initial conditions and skip the initial operating point solution. (uic on the .tran Spice directive)
 

Thread Starter

Ziin13

Joined Mar 4, 2013
10
@Papabravo
@Bordodynov

Thanks for the explanation. I was able to get my simulation going, but I don't understand how the 2 SPICE directives help. Do you have insight how it works?

.ic v(VCC) = 0
.opt cshunt=1f gshunt=1n

1634150881043.png
 

Papabravo

Joined Feb 24, 2006
17,029
Yes, I can see exactly what is going on.

.ic is the Spice directive for setting an initial condition. This is one of the things that Spice does when computing the DC operating point at the beginning of the simulation. Because the UIC parameter in the .tran directive has said to skip the operating point calculation, you must supply an explicit value. The .ic Spice directive is explained in the LTspice Help file.

The "options" specified in the .opt directive are also explained in the LTspice Help file.
cshunt is the optional capacitance that is added from every node to ground. It has the value of 1 femtofarad (1E-15), which is very tiny.
gshunt is the optional conductance added from every node to ground. It has the value of 1 nanosiemens (1E-09), which is equivalent to a 1 Gigaohm resistance
The 4th parameter in the .tran directive sets the maximum timestep to 100 μsecs.

Recommendations
  1. Read the LTspice Help file from beginning to end
  2. Do 1. at least 2 more times, and take notes.
 
Last edited:

Papabravo

Joined Feb 24, 2006
17,029
Hi Bordodynov

There is no VCC.
Why the .IC V(VCC)=0 statement?
Check the schematic in Post #4 (Bordodynov's post)
Vcc is the net label on the net between the resistor R3 and the opamp U1. The TS did not add this change to his schematic. One might conclude that it didn't hurt anything even if it had no effect. The tiny capacitor, cshunt, and the big resistor, gshunt, probably did the job all by themselves.
 
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Thread Starter

Ziin13

Joined Mar 4, 2013
10
@Papabravo
Thanks for the explanation and suggestion.

Unfortunately, I ran to the same error when scaling up my circuit using 3 different op-amps. I simulated each op-amp separately to ensure they all are working, but it no longer works when adding them together.

During my simulation on just OPA170 circuitry alone, I notice that the .opt cshunt=1f gshunt=1n causing the 'Time step too small". It only works when I don't use the .opt cshunt=1f gshunt=1n.

Any suggestions?

1634223599597.png

Attachment is my schematic and component library for your reference.
 

Attachments

Last edited:

Papabravo

Joined Feb 24, 2006
17,029
If you use the UIC option on the .tran command, you may need to extend the initialization of the power pins to the other opamps. You also have a net with two different names. The power pin of U1 is named VCC and it is connected to a net named 3.3V.
 
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