Hi guys,
I'm working on a project that requires an SR flip-flop. I have a couple of unused gates on a CD40106 Schmitt inverter chip, so the plan is to add some diodes and resistors to make a couple of NOR gates (as described here) then feed them back into each other to create the flip-flop.
This is causing a problem in my LTSpice simulation though. It's fine until I connect the feedback path, at which point it gets stuck on "Damped Pseudo Transient Analysis", which I understand means a convergence failure.
Is there a Spice directive I can add to fix this? I don't care which state the flip-flop starts off in.
I'm working on a project that requires an SR flip-flop. I have a couple of unused gates on a CD40106 Schmitt inverter chip, so the plan is to add some diodes and resistors to make a couple of NOR gates (as described here) then feed them back into each other to create the flip-flop.
This is causing a problem in my LTSpice simulation though. It's fine until I connect the feedback path, at which point it gets stuck on "Damped Pseudo Transient Analysis", which I understand means a convergence failure.
Is there a Spice directive I can add to fix this? I don't care which state the flip-flop starts off in.