LTSpice: CD40106 convergence problem

Discussion in 'The Projects Forum' started by bearblock, Oct 4, 2013.

  1. bearblock

    Thread Starter Member

    Oct 24, 2008
    Hi guys,

    I'm working on a project that requires an SR flip-flop. I have a couple of unused gates on a CD40106 Schmitt inverter chip, so the plan is to add some diodes and resistors to make a couple of NOR gates (as described here) then feed them back into each other to create the flip-flop.

    This is causing a problem in my LTSpice simulation though. It's fine until I connect the feedback path, at which point it gets stuck on "Damped Pseudo Transient Analysis", which I understand means a convergence failure.

    Is there a Spice directive I can add to fix this? I don't care which state the flip-flop starts off in.
  2. SgtWookie


    Jul 17, 2007
    First, it would help if you uploaded your .ASC file to the forum as an attachment (click the "Go Advanced" button, then "Manage Attachments"... .asc is an allowed filetype.)

    Try editing the simulation command (you can just right-click on the .tran line) and check the box next to "Start external DC supply voltages at 0v". Next, try using .ic (initial condition) statements to set nodes at voltages prior to running the simulation.
    You could skip the initial operating point solution (last box) but that can cause some strange results.
  3. ronv

    AAC Fanatic!

    Nov 12, 2008
    You might try - edit spice analysis - skip initial operating point.
  4. bearblock

    Thread Starter Member

    Oct 24, 2008
    Here's the .asc file.

    I tried startup and uic without any success - I guess this is because the CD40106 model I'm using doesn't have a VDD pin, you just set the supply voltage as part of the Spice command?

    It's fixed now, using initial conditions. I'd previously tried just setting one output of the flip-flop, which didn't work, but if I set one low and one high it works perfectly. Thanks!