# Logic Question about timing diagram

Discussion in 'The Projects Forum' started by Padderick, Jan 16, 2013.

Jan 7, 2012
11
0
Hi all together,

I have added a timing diagram as PDF and hope you can help me to find a solution for the following problem.

In my project i get the output A at one comparator output and the output B at another comparator.
From this two outputs I want to get the signal Q but I do not know what is a good way with less delay.
I need a hardware circuit because the delay time should be maximum around 100 until 300 ns.

If you have got an idea to solve this problem it would be nice to get known about this.

Thanks,

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2. ### WBahn Moderator

Mar 31, 2012
23,384
7,096
This is going to require a state machine because just knowing the inputs is not sufficient. For example, if A is HI and B is LO, Q might be HI (time index t1+) or Q might be LO (t2+).

Are the inputs guaranteed to be as shown, namely that B will go HI and return LO only while A is HI? Is there a minimum amount of time that can be relied on between A going HI and B going HI? Similarly, is there a minimum amount of time that can be relied on between B going LO and A going LO? What about the minimum time that A will be LO or that B will be HI.

3. ### ErnieM AAC Fanatic!

Apr 24, 2011
7,957
1,827
Looks to me you may get away with just a toggle flip flop with a clock derived from (A and not B).

However, that leaves a synchronization problem open.

Brain now empty... NEXT !!!

4. ### WBahn Moderator

Mar 31, 2012
23,384
7,096
I wouldn't recommend going that route specifically because of the synchronization problem you noted.

Note that it also assumes that A and B make glitch-free transitions. That may or may not be a reasonable assumption -- the OP will need to provide more info about where A and B come from.

But unless there is a high-speed (say 20MHz or so) free running clock available, we probably have to make that assumption.