Hi i am starting to study Logic gates in my computer science course and I am just a little confused in regards to this particular logic gate:

This is a simple flip-flop gate, R & S being for input and Q for output. However I do not understand, what the input would be for the second input on the first pass for each NAND gate. For example, say the first input is 1 1, so 1 into R and 1 into S. What about that second input that flows into each NAND gate??? I understand that after the second pass onwards the second input come from the ouput of the other gate. But what about that first pass of 1 1, is there a default value of 0 if there in no input? thankyou for any help in understanding this matter.

 

For an S-R latch, R=S=1 is an illegal state. Think about it R is for Reset and S is for Set, so when R=S=1 you are setting and resetting the latch.

The following section in the AAC e-book should explain the deeper workings of the S-R latch: http://www.allaboutcircuits.com/vol_4/chpt_10/2.html

You will notice your latch has two NAND gates where as the tutorial looks at the latch with two NOR gates - do not be confused about this, the operation of the latches is identical except that the latch you posted is an active low latch, i.e. Q = NOT(Set) AND Reset. Whereas the one in the tutorial is an active high latch, i.e. Q = Set AND NOT(Reset).

Dave

 

Hi Dave thankyou for your prompt reply. However what I'd like to know is for example, say that the input into these gates is; S = 0 and R = 1(or any valid input, dosen't matter), but each NAND gate needs two inputs to operate on!. Where is that second input coming from on the very first pass of this circuit BEFORE there is an output from the other NAND gate(whether it be from the bottom or top NAND gate). Since there is no output yet from either gate is there just a default value of '0' as the 2nd input?? Thankyou.

 

It is an error to assume that a logic gate "requires" two inputs in all cases. If you look at the DeMorgan equivalent of the NAND gate it becomes clearer.

NAND: A high and a high is a low
DeMorgan Equivalent: A low or a low is a high

In an OR gate only one input needs to be in a defined state for the output to be determined. The other input may be a don't care.

 

Hi Dave thankyou for your prompt reply. However what I'd like to know is for example, say that the input into these gates is; S = 0 and R = 1(or any valid input, dosen't matter), but each NAND gate needs two inputs to operate on!. Where is that second input coming from on the very first pass of this circuit BEFORE there is an output from the other NAND gate(whether it be from the bottom or top NAND gate). Since there is no output yet from either gate is there just a default value of '0' as the 2nd input?? Thankyou.

This isn't an easy one to explain, but I'll have a go. To get the full answer to this you need to look at the CMOS implementation of the clocked SR latch (sorry I couldn't find one through Google). The clock and its complement feed the gates of two transistors in the two pull down paths, which are serially connected to the inputs of two CMOS inverters. The clock transistor is in series with the Set transistor in one path, and the clock complement is in series with the Reset transistor in the other path. The W/L ratios of the clock and Set transistor are designed as such that they can supply sufficient current with which to pull the inputs to the CMOS inverters below the gate thresholds for that inverter. This will automatically pull Q to one level (either Vdd = 1 or GND = 0 dependant on whether the latch is active high or active low), and consequently due to the cross connections of the latch circuitry will pull NOT(Q) to the complement of Q.

Sorry it sounds a little confusing, but the short answer is that the latch is designed at the transistor level to pull the outputs Q and NOT(Q) to default levels dependant on whether the latch is active high or active low.

Dave