Logic Analyzer Help! (Logic Cube)

Discussion in 'Digital Circuit Design' started by spinnaker, Dec 26, 2010.

  1. spinnaker

    Thread Starter AAC Fanatic!

    Oct 29, 2009
    I purchased a Zeroplus Logic Analyzer and I think I made a mistake. It gets very good reviews but the documentation is horrendous! There seems to be no tutorial or support forum that I can find.

    I basically bought the thing as a toy and a learning experience.

    Basically I know very little about logic analyzers.

    If no one here has a Logic Cube, maybe these things are generic enough to provide some help. I have included a screen shot of my screen.

    What I am trying to do is to analyze the data sent to an LCD screen. I am sending the letter Z over and over to the LCD in 4 byte mode, so I should be seeing a 0x5 and 0xA.

    I grouped my 4 data bits into a bus and trigger off the enable pin of the LCD. I am using the analyzer for a clock and it is set to 1MHZ. My PIC is running at 250khz.

    I am indeed seeing the 0x6 and 0xA but I am also seeing a bunch of other data. If you look at the screen shot, there are several transitions after the 0xA. They are 0xD, 0x9 and 0xB. I have circled these in the attached picture.

    I have tried triggering on a high enable, going high and going low. All seem to have similar results.

    Also I ungrouped the bus into channels and it looks like data is being captured when enable is low. Now I know data does start to be captured until enable goes high but I thought that no data would be captured unless the trigger was high.

    When I run repetitive, very little data seems to be captured. Why is this?

    Also in repetitive run, I can see my enable going high and when it does, the appropriate data lines are high but I still get a lot of garbage data that shoes up when enable is low.
  2. spinnaker

    Thread Starter AAC Fanatic!

    Oct 29, 2009
    Ah I think I got it. I needed to filter on enable as well as trigger. Plus I am now capturing a lot more data too.

    Still what was that garbage data when enable was low?
  3. eblc1388

    AAC Fanatic!

    Nov 28, 2008
    I don't have the Logic Cube but all logic analysers should work the same. What you are seeing are the small difference in timing when port pins toggle states. Without capacitance on the port pin, they should go high/low together. This is not the case as other physical connections are made to the port pins.

    Sampling at 16 times(1Mhz/(250KHz/4)) the PIC instruction cycle frequency, the analyser is tell you that the port pins voltage actually changes with small timing difference between them.

    You also don't need to sample at 16 times the PIC instruction frequency(62.5KHz) as it is too fast. The port pin can only change state every 16 sampling and this would cut your effective storage buffer length to 16 times shorter, i.e. 16 times less amount of useful samples stored.

    You would get more useful data if you sample at two times the instruction frequency of the MCU.
    spinnaker likes this.
  4. spinnaker

    Thread Starter AAC Fanatic!

    Oct 29, 2009
    Thanks eblc!

    Your brief paragraph is many times more informative then the couple of hundred pages of the manual. You should write for ZeroPlus! :)

    The manual says I should sample 4 times the clock frequency.

    According to your instructions, my sampling frequency should be 125K. But the software only allows to pick from a list of set frequencies. The nearest to 125K is 100khz and 200khz.

    Should the software allow and frequency?

    Should I be clocking off of my enable pin instead of triggering off of it? But I have the same problem as I only have set frequencies. And I can see where I might have a problem determining pulse width with an intermittent clock.

    I hope you don't mind answering some dumb questions. I have a few here and may have more.

    1. The display shows some fixed bars, Ds, T and Dp. I am guessing Ds is Data Start? What is T and Dp?

    2. I have a Trigger Position, Trigger Page and Trigger Count settings. Where would I use those?

    3. I have a setting for RAM size. I have settings of 2K, 16K and 32K. I assume this is the amount of data being sampled. Why would I just not always set it to the max? Why is it limited to 32K and not the memory size of the PC? Or is this just the on board buffer?
  5. eblc1388

    AAC Fanatic!

    Nov 28, 2008
    It really doesn't matter if the sampling frequency is faster than the clocking of the circuit. So I would say both 100Khz or 200Khz will be fine.

    Normally one should be triggering via a known event, and "Enable" level change is such event. If timing between events is important to you then you can sample at a slightly faster frequency like 4x clocking speed. For PIC, this is the frequency of the xtal or external clocking input.

    They would be timing markers which you can place anywhere in your captured data. Once you have placed these markers, then the software will calculate the timing difference between these markers.

    You have to consult the ZeroPlus manual to know exactly what these markers are and how to place/move/remove them from the display.

    These are aids to let you specify exact where the capturing of data into into LA memory buffer will start.

    Because the logic analyser capture buffer "depth" is limited, and the capturing frequency is high, it can easily overflowed by capturing data one don't want. The secret is to capture the part of the data stream that you actually wanted.

    The trigger count settings would allow the analyser "not to capture" the logic state unless all these user conditions are met. So if you set the trigger count to three, it will only start to capture after it see the triggering condition for the third time.

    This is the length or more commonly known as "depth" that you can store your "samples". Note, this is very different from "data" that you have assumed. Once you have set the sampling frequency and depth of buffer, the total "capturing time" after the trigger condition is then fixed. The faster the sampling frequency, the shorter this length of time is. You would want the part of the logic change you wanted to examine falls within this period.

    If you set the sampling frequency very fast, you will be storing samples that remains stable in between many samples. This would be a waste of your LA resources for no good purpose. Obviously you would want to sample just fast enough to let you capture all the important logic changes in your circuit and have the longest stream of captured data in your display.

    It is limited to 32K(or 1M for some expensive LA) because the LA has to sample very fast, like 50MHz or 100Mhz. The real time data cannot be sent to the PC in real time via the usual ports like serial or USB. The sampled data is stored first in fast SRAM in the LA and then transferred back to PC after the capturing event, with time stamps.

    It you want to have continuous sampling for very long depth, some USB LA can do real time sampling to great depth but the maximum sampling frequency will be limited to 24Mhz max. and sometimes much less. Examples of these LA are USBee and Saleae.