I've been trawling the internet for a passive battery balancing circuit and came across one I am happy with. See attached - not my circuit credit elsewhere. For my application I am installing the battery pack and balancing circuit together. I have run some simulations and it seems current is consumed at idle (legs with R1 & R3 etc).

The schematic image attached is my circuit. I am not sure if it is a valid n channel mosfet circuit (Q3 & Q6). While it does simulate ok in Multisim I do no trust it as it does not seem right!

The circuit works as follows:
regulated and controlled power comes in by H1 (CV & CC at 8.4V)
the circuit is divided into 2 cells
if the cell voltage is high power is shunted
when H1 is disconnected the passive balancing circuits are also disconnected.

 

Q1 and Q4 ,are drawn wrong way round, emitters to positive.

 

Quite right. Thanks. Will sort that out later and post an update sch.

 

Q1 and Q4 ,are drawn wrong way round, emitters to positive.

Yes. If you have the PNP transistors connected this way in real life, you will be using the reverse PNP transistors, which might kind of work, but not well. Possibly your simulator model didn't characterize that behavior well.

 

Pins changed around for those 2 transistors and new schematic below.

What are the thoughts about Q3 and Q6 as a method of stopping current leak when not plugged into charge at H1?