Hello,

I am trying to build a linear voltage regulator using mos and opamp. During the process, I noticed that if I connect the source of a P mos to the + powersupply and drain as the output, as soon as I connect the output to a load the output drops (2.5v->0.8V). Also, I observed form my scope that there is a triangle wave oscillation at the gate of the mos. However, if I use N mos ,connect drain to + and use source as the output, then I get a very stable non-oscillating output. Can someone tell me why the oscillation happen? If I use mos in switch mode there is no difference if I put the load at the source or drain but why in linear mode I should use drain as the output?

best
LEE

 

Need a schematic of your circuit to better understand your dilemna.

hgmjr

 

Hello,

I am trying to build a linear voltage regulator using mos and opamp. During the process, I noticed that if I connect the source of a P mos to the + powersupply and drain as the output, as soon as I connect the output to a load the output drops (2.5v->0.8V). Also, I observed form my scope that there is a triangle wave oscillation at the gate of the mos. However, if I use N mos ,connect drain to + and use source as the output, then I get a very stable non-oscillating output. Can someone tell me why the oscillation happen? If I use mos in switch mode there is no difference if I put the load at the source or drain but why in linear mode I should use drain as the output?

best
LEE

Need schematic. Using a PMOS device to build a linear means it is an LDO and has to be carefully compensated or it will oscillate. You may have just gotten lucky with the N device and it was stable, but it also needs compensation.

 

here is the sch

 

here is the sch

My professor told me that the reason using source as a output is better is because the current flow is depend on Vgs so if source voltage, there is a feed back to let more current through thus opamp dont have to do many hard work to re-balance the output

 

Why did you post the circuit that works?

 

Why did you post the circuit that works?

Here is the one that oscillates ...

 

The circuit with the PMOS likely oscillates because of the added voltage gain of the common-source amplifier which affects the phase-margin. The NMOS circuit source-follower output adds no voltage gain so it is stable.

To make the PMOS circuit stable you will need to add some high-frequency rolloff at the op amp output.

 

Here is a way to compensate this type of circuit. You may have to play with the values of the added parts. If it were my circuit, I would put it on a simulator and cap-couple a 1kHz, 100mV p-p square wave to pin 2 of the op amp. I would also add a 10k resistor in series with the pot that's across the zener. Then I would monitor the circuit's output and adjust the compensation for minimum overshoot and ringing.
You should split R3 into 2 equal series values, and add a big capacitor (100uF or more) from the junction of these two resistors to ground. This will reduce the amount of input ripple that gets imposed on the zener.

EDIT: I put one of the resistors in the wrong trace. Doh!
Fixed now. I have to confess, though, that I don't know for sure if this will work.

 

Here is the one that oscillates ...

here is why (it is not compensated):

http://www.ti.com/lit/an/snva167/snva167.pdf

http://www.ti.com/lit/an/snva246/snva246.pdf

 

Here is the one that oscillates ...

Here is an example of a working P-FET regulator showing the compensation it needs around the op amp. It uses a PWM signal to derive the voltage reference but the operation of the regulator is the same as if it were tied to a fixed voltage. LDO regulators must have compensation around the error amplifier.

C2, R5 and R7 are compensation components.

NOTE: C5 (the output cap) is also important for compensation as it's ESR must be enough. That is why a Tantalum cap is specified.