why would you try to slow down the fet even more? What purpose does increasing the gate capacitance serve? Are you sure you read the original circuit correctly?I added a .1uf and 10uf capacitor on the gate of the FET
why would you try to slow down the fet even more? What purpose does increasing the gate capacitance serve? Are you sure you read the original circuit correctly?I added a .1uf and 10uf capacitor on the gate of the FET
Ron your amazing your setup worked. I did add a variable to the mix though since I used a different FET and it is logic level. I dropped the circuit's input to 5V instead of 10V. I really don't think that will make a difference once my new fets show up. Your setup created the first FET to survive the full 60 volts at 1.3 amps out of the 5 or 6 I had tried. This particular fet wasn't rated as well so I didn't want to push it to the full 1.6 amps but it made it past where I have been so far! Thanks for modeling that out and figuring this out whole thing out.I agree. The gate resistor and capacitor add a pole in the loop, in addition the the op amp's pole. This is why it was unstable. Adding the 100nF cap pushes the external pole to a lower frequency, but probably not far enough to overwhelm the internal pole.
Try changing the gate resistor to 100Ω, and the resistor in the feedback path to 10k. Add 100pF from op amp output to inverting input.
EDIT: I didn't make it clear that you need to omit the cap from gate to GND.
Meant to do this all in one message. I am novice to electronics and was trying to model after a product that I knew worked. I now understand how the capacitors can slow these loops down but didn't know that going into this.why would you try to slow down the fet even more? What purpose does increasing the gate capacitance serve? Are you sure you read the original circuit correctly?
Excellent! The 100pF cap, BTW, actually "speeds up" the loop, in that it provides a high frequency path that bypasses the lag caused by the MOSFET gate capacitanceRon your amazing your setup worked. I did add a variable to the mix though since I used a different FET and it is logic level. I dropped the circuit's input to 5V instead of 10V. I really don't think that will make a difference once my new fets show up. Your setup created the first FET to survive the full 60 volts at 1.3 amps out of the 5 or 6 I had tried. This particular fet wasn't rated as well so I didn't want to push it to the full 1.6 amps but it made it past where I have been so far! Thanks for modeling that out and figuring this out whole thing out.
Thanks everyone for all the input.
Maybe I can start an actual build thread for my full device.
by Duane Benson
by Jake Hertz
by Duane Benson
by Jake Hertz