My question is how do I know which inputs and outputs need to be
declared? In the example code intsig is not in the port list, why? Is this
because it is only used internal to the module, and if so no internal
ports need to be in the list as it is not a in or output to the module? It is declared in the code as: "reg out, intsig;"
I have included a module example.
top_ver.v
module top_ver (q, p, r, out);
input q, p, r;
output out;
reg out, intsig;
bottom1 u1(.a(q), .b(p), .c(intsig));
bottom2 u2(.l(intsig), .m(r), .n(out));
endmodule
declared? In the example code intsig is not in the port list, why? Is this
because it is only used internal to the module, and if so no internal
ports need to be in the list as it is not a in or output to the module? It is declared in the code as: "reg out, intsig;"
I have included a module example.
top_ver.v
module top_ver (q, p, r, out);
input q, p, r;
output out;
reg out, intsig;
bottom1 u1(.a(q), .b(p), .c(intsig));
bottom2 u2(.l(intsig), .m(r), .n(out));
endmodule