I was recently reading about metastability in flops, and I assume this is also applicable to latches, and was wondering why general purpose I/Os on MCUs/DSPs don't worry about this?
When I configure a pin to be an input that is driven asynchronously, however internally it is sampled from its own synchronous clock, could there not be moments of metastability as it latches the data pins into a register (I am basing my premise here, on the fact that registers are just latches/flops).
Cheers
When I configure a pin to be an input that is driven asynchronously, however internally it is sampled from its own synchronous clock, could there not be moments of metastability as it latches the data pins into a register (I am basing my premise here, on the fact that registers are just latches/flops).
Cheers