Latches/Flip flops - Metastability

Thread Starter

Skeebopstop

Joined Jan 9, 2009
358
I was recently reading about metastability in flops, and I assume this is also applicable to latches, and was wondering why general purpose I/Os on MCUs/DSPs don't worry about this?

When I configure a pin to be an input that is driven asynchronously, however internally it is sampled from its own synchronous clock, could there not be moments of metastability as it latches the data pins into a register (I am basing my premise here, on the fact that registers are just latches/flops).

Cheers
 

mik3

Joined Feb 4, 2008
4,843
It can happen in MCUs/CPUs too. However, there are some techniques which reduce the possibility of metastability to happen.
 

Papabravo

Joined Feb 24, 2006
21,306
If you look at a typical pin diagram you'll see that input latches are actually rare for a PIC or an AVR. Many ASCIC designs have two or three stage syncronizers on asynronous input pins. The use of a three stage syncronizer lowers the probability that a metastable event will make it through all three stages to a very small number.

If you look at the internal design of clocked Flip-Flops you will see that they indeed have multiple stages.

Latches are a good deal simpler and the main strategy here is to include a redundant covering term which you must prevent an optimizer from removing.
 
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Thread Starter

Skeebopstop

Joined Jan 9, 2009
358
If you look at a typical pin diagram you'll see that input latches are actually rare for a PIC or an AVR. Many ASCIC designs have two or three stage syncronizers on asynronous input pins. The use of a three stage syncronizer lowers the probability that a metastable event will make it through all three stages to a very small number.

If you look at the internal design of clocked Flip-Flops you will see that they indeed have multiple stages.

Latches are a good deal simpler and the main strategy here is to include a redundant covering term which you must prevent an optimizer from removing.
Ok I see. So that is good for data integrity, but what about all of these potential 1st stage metastable events occuring and their impact on EMC? I suppose as it is in silicon the trace length is so minute that acting as an antenna is considered negligible?

Cheers
 

Papabravo

Joined Feb 24, 2006
21,306
I don't see that metastability has anything in particular to do with EMC. The inability to decide on a stable state is like wandering around in the wilderness. High frequency oscillation would probably be a good thing since it would quickly drive the output to a stable state.

The experiment on a single flip-flop is to adjust two pulses relative to each other and watch what happens as the data edge violates the setup and hold time conditions of the flip-flop relative to the clock pulse.

The output might drift around for a while or you might get a runt pulse. All in all it is getting more difficult to create and observe these conditions.
 

leftyretro

Joined Nov 25, 2008
395
I guess I could use a context definition of metastability. I think you are asking how flip flops (or any sampled logic circuit) deals with possible input signal 'race conditions' and as PB said it is defined in the setup and hold timing specifications for the specific flip flop isn't it?

Lefty
 

Thread Starter

Skeebopstop

Joined Jan 9, 2009
358
I guess I could use a context definition of metastability. I think you are asking how flip flops (or any sampled logic circuit) deals with possible input signal 'race conditions' and as PB said it is defined in the setup and hold timing specifications for the specific flip flop isn't it?

Lefty
Correct, but it can end up looking like a high harmonic oscillation before it settles down again, which would be a regular occurence in asynchronously sampled digital I/O. As they said though, just string in more latches/flops to reduce the probability of an occurence sneaking through.
 
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