# Latch with NOT gates

Discussion in 'Homework Help' started by screen1988, May 10, 2013.

1. ### screen1988 Thread Starter Member

Mar 7, 2013
310
4
I have a latch with NOT gates as in the picture.

Let's assume that initially, switch is connected to Vcc then I have:
Input of upper NOT is 1 (logic)
Output of lower NOT is 1
Now if I look at the upper NOT:
Because its input is 1 => its output Q = 0
Next consider the lower NOT:
I am confused about the two possibilities bellow. Which one is right?
1)
Because input of the lower NOT is Q = 0 (result from upper NOT)
=> its output $\overline {Q}$ = 1
2)
Because output of lower NOT $\overline {Q}$ = 1 => its input has to be 0.
I mean that it is output of the lower NOT that cause its input to be 0.
I think #2 is maybe wrong because the input of NOT isn't affected by its output but not sure.

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2. ### MrChips Moderator

Oct 2, 2009
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You have to focus on cause and effect.

The cause is the INPUT.
The effect is the OUTPUT.

The circuit is called a bi-stable because it has two stable states.
It works because it is a positive feedback system, i.e. the input is reinforced by the output of the system. It will latch up to either logic LOW or HIGH when forced to do so.

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3. ### Ramussons Well-Known Member

May 3, 2013
742
126
Let's look at it this way:
Output Depends on Input; Not the other way!

"I think #2 is maybe wrong because the input of NOT isn't affected by its output but not sure."

Your thinking is Correct. #2 is wrong.

Ramesh

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4. ### Papabravo Expert

Feb 24, 2006
11,678
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You can't really build a latch with NOT gates. It forces you to connect an output (Q*) to Vcc or GND. That is a bad business, an output trying to short a supply to GND or vice versa.

Latches are almost ALWAYS built with 2-input NAND gates so the complementary outputs can be connected to gate inputs and outputs won't fight with switches wired to Vcc or GND.

I hope you were only simulating this circuit and not trying to use it to short your power supplies to GND!!

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5. ### Jony130 AAC Fanatic!

Feb 17, 2009
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Yes we can, but we need to add two resistors and two diodes.

6. ### MrChips Moderator

Oct 2, 2009
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I see nothing wrong with this design.

7. ### WBahn Moderator

Mar 31, 2012
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Actually, using cross-coupled inverters as an SRAM cell is common practice in CMOS IC design. There are many variants. Sometimes you use a weak inverter for one of them that you can easily overdrive with a tri-stated data signal. We commonly used an NFET on each output and would turn on whichever signal we wanted taken LO. Frequently you buffer the output to prevent follow-on circuits from upsetting the latch, but sometimes you just don't have room for that and so you carefully design how it interacts with the follow-on circuits.

8. ### Ron H AAC Fanatic!

Apr 14, 2005
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So, with typical logic gates, you get a few mA or tens of mA for a few nanoseconds each time the switch toggles. Not a big deal.

9. ### Papabravo Expert

Feb 24, 2006
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I still maintain that connecting an output to a voltage source is a silly thing to do, but whatever.

10. ### WBahn Moderator

Mar 31, 2012
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It some ways its actually less silly than the notion of an open-collector output when you think about it (at least think about it in a certain way). In the case of an open-collector output you have a device that is trying to assert a HI (the resistor) and you overdrive it with a device that can assert a LO more strongly (the gate output). But both devices remain in contention for the entire time that you are asserting a LO. In this case, you have a device that is trying to assert one logic level (an inverter) and you overdrive it with a device that can assert a possibly different logic level more strongly (the supply). The difference here is that the inverter responds immediately to agree with the overdriven signal and there is no longer any contention.

11. ### screen1988 Thread Starter Member

Mar 7, 2013
310
4
Can you explain the reason for this?
Do you refer to the case when input is floating?

12. ### WBahn Moderator

Mar 31, 2012
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You need to read the whole thread more carefully. This is addressed in some detail. Do that and then, if necessary, ask for specific clarification on points that are still unclear.

13. ### Papabravo Expert

Feb 24, 2006
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No, my point was that the alternative of using 2-input gates to make a latch exists, and avoids the problem of connecting an output to either Vcc or GND.

The counter opinion is that the momentary fault is of no particular concern and that a latch built with inverters is a "???" practice. I'm not sure what word to use in this context.

14. ### MrChips Moderator

Oct 2, 2009
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I have no concern with using two NOT gates in this fashion and I have seen it used to debounce SPDT push-buttons on commercial/industrial instruments.

Edit: Except the push-button is wired differently. The center connection is wired to ground and the two contacts are wired to the inputs of the two inverters.

Last edited: May 15, 2013
15. ### screen1988 Thread Starter Member

Mar 7, 2013
310
4
I have re-read many times but I almost have no idea what you are trying to say.
Here is a latch from NOT gate:

And I think here is the circuit that Jony suggest:

Could you tell me where the problem you are talking?

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16. ### MrChips Moderator

Oct 2, 2009
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This is what I mean:

17. ### WBahn Moderator

Mar 31, 2012
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"???" => "common and accepted"

would be my best offering.

18. ### Papabravo Expert

Feb 24, 2006
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Those words were never applied to such a concept in my experience with traditional TTL. Maybe things are different now on chips. I have seen chip designers do unusual things, for sure.

19. ### MrChips Moderator

Oct 2, 2009
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I cannot see anything wrong with this circuit application. Why do you object to this?

20. ### Papabravo Expert

Feb 24, 2006
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Well I've explained it at least twice. I don't have the energy for a third shot.