Kvl-kcl

WBahn

Joined Mar 31, 2012
30,057
The beautiful thing about so much of engineering is that once you find an answer to a problem, you can usually verify the validity of that answer from the answer itself.

So in this case start with the output voltage you found and assume that it is correct. The walk it back through the circuit determining the voltages and currents as you go and then see if you end up with 4mA flowing downward in the left-most branch. If you do, then you have the correct answer. If not, then you don't.
 

WBahn

Joined Mar 31, 2012
30,057
You need to work on being neater with your work and tracking your units.

You use I1 in the equation for Loop I (and I5 in the equation for Loop III) but you never define either of them on the diagram. In particular, you don't indicate what direction they are defined to be.

Redo your math for Loop II.

If you are going to do the math along the way, you need to be sure to keep sufficient sig figs in the intermediate results. The rule of thumb in engineering is to report results to 3 sig figs. This means that intermediate results should have at least 4 and preferably 5 sig figs. Some of your results are barely 1 sig fig. Even if you had done the algebra correctly your intermediate results would have left you with a nearly 6% error in your answer. That's about 50 times what should be acceptable.
 
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