Assalm-u-alaikum!
Actually i have a project.please help me in this project.
Mu project is following.
please tell be the test benches of this project.
Modify the KEYPAD scanner circuit (section 5.18) for a stopwatch.
i) 2 x 3 KEYPAD.
ii) Keys are START, STOP, RESET, INC, DEC, CLEAR.
iii) Every key generates different opcode.
iv) Key functions are as under
Key Name Code Description
START 000 starts the stop watch
STOP 001 holds the value of stop watch
RESET 010 resets the stop watch
INC 011 increments the value of stopwatch by 100sec (startup value)
DEC 100 decrements the value of stopwatch by 10sec (if INC is used before)
CLEAR 101 clears the startup value (entered by INC/DEC at startup)
a) Draw an Algorithmic State Machine (ASMD) chart.
b) Give Verilog behavioral model to synthesize the FSM described in part (a).
c) Develop a comprehensive Test Bench for part (b)
Actually i have a project.please help me in this project.
Mu project is following.
please tell be the test benches of this project.
Modify the KEYPAD scanner circuit (section 5.18) for a stopwatch.
i) 2 x 3 KEYPAD.
ii) Keys are START, STOP, RESET, INC, DEC, CLEAR.
iii) Every key generates different opcode.
iv) Key functions are as under
Key Name Code Description
START 000 starts the stop watch
STOP 001 holds the value of stop watch
RESET 010 resets the stop watch
INC 011 increments the value of stopwatch by 100sec (startup value)
DEC 100 decrements the value of stopwatch by 10sec (if INC is used before)
CLEAR 101 clears the startup value (entered by INC/DEC at startup)
a) Draw an Algorithmic State Machine (ASMD) chart.
b) Give Verilog behavioral model to synthesize the FSM described in part (a).
c) Develop a comprehensive Test Bench for part (b)
