Hi there,
I've found in my circuit that my JK flip-flop "Q" output is stuck at logic 1.
I've probed the input feeds to the "J" , the "K" and the clock inputs and they appear to be functioning correctly.

Could the only cause of "Q" being stuck at logic 1 be a short circuit between say the "J" or "K" input to the "Q" output?

Many thanks,
Matt

 

Or if your power is connected incorrectly or is otherwise wrong, or your set and/or reset lines, or the chip is bad.

 

Just checked and the power is connected fine and correctly. Set and reset lines aren't being used either, nor an IC just using a JK flip-flop. As I'm simulating it at the moment. Its a count-down counter by the way.

So would I be correct in saying that after ruling the other potential causes out that there could be a short circuit between the "J" or "K" input to the "Q" output right?

Many thanks,

Matt

 

If you are simulating it, then no because J and K are working correctly. If it were shorted, you would see issues with J and/or K.

 

Just checked and the power is connected fine and correctly. Set and reset lines aren't being used either, nor an IC just using a JK flip-flop. As I'm simulating it at the moment. Its a count-down counter by the way.

So would I be correct in saying that after ruling the other potential causes out that there could be a short circuit between the "J" or "K" input to the "Q" output right?

Many thanks,

Matt

If you dont use the preset and clear you should connect them to ground if they are active high as i suspect. This is because if you use TTL chips a floating input is taken as high due to the internal construction of the chips. If it is CMOS chip the inputs should be never left floating because you wont know if they are high or low.

 

If you are simulating it, then no because J and K are working correctly. If it were shorted, you would see issues with J and/or K.

Yes, but the circuit I've been given has deliberately had faults enabled using Workbench, in order for me to fault find.

So could it still be as I originally suspected?


Many thanks

 

What jk FF is being used?

Can you post a diagram of the circuit? [hint: ctrl or alt print screen, paste into paint, save as jpg].