JK FF in Orcad

Discussion in 'General Electronics Chat' started by jag1972, Mar 2, 2010.

  1. jag1972

    Thread Starter Active Member

    Feb 25, 2010
    Hello Folks,
    I have a problem trying to simulate a simple sequential circuit in Orcad capture (previously know as PSpice). Infact I have no problem with the circuit, I do have a problem with setting the JK flip-flop up. I am using the 74LS76 (JK flip flop with preset and clear), had a look at the data sheet and the characteristic table implies that as long as both preset and clear are taken high the should cause Q to be 0. After that the flip flop should change on the falling edge of a clock pulse; however my output trace does not reflect the JK flip flop characteristics too well.

    My settings are as follows:

    Preset and clear both taken high, clock set to a frequency of 10 Hz (50ms low and 50ms high).
    J and K inputs are connected to STIMS, which cycle through all combinations at 100ms time frames.

    J = 0, 1, 0, 1 and
    K = 0, 0, 1, 1

    Q should be: 0, 1, 0, Toggle

    I would very much appreciate any help or advice that you could offer :)

  2. kkazem

    Active Member

    Jul 23, 2009
    Hi, In order for me to help you, I need a copy of your PSPICE (ORCAD) netlist, and a copy of the file with the JK flip-flop

    model you're using. But before we get to that, I found some discrepancies that I need you to clear-up with me so I can help

    you. First, please look at this TI datasheet for the SN74LS76A, http://focus.ti.com/lit/ds/symlink/sn74ls76a.pdf , please

    notice on the first page that the SN74LS76 loads the Master (Recall, that the JK is a 2-stage FF with master and slave

    sections) of the JK on the Rising Edge of the clock, then transfers the Master Output the Slave Input on the

    falling-clock-edge. It seems that you interpreted the datasheet as saying that it should change state on the falling clock

    edge, and it does, however, the J & K signals must be stable before the rising-clock-edge and remain stable until after the

    falling-edge of the clock. It is true that for your purpose, the Preset\ & Clear\ Inputs (both async, & inverted logic

    inputs) must be high at all times during your simulation (except perhaps for doing an initial clear to get Q=0), and the

    74LS76 will only have a guaranteed Q=0 state initially if the Preset\ & CLR\ = Hi, then the CLR\ is pulsed low for >= 20

    nSec. During this operation, the CLK, J, & K inputs are all = X (don't care). It is NOT TRUE that Q= Low if the Preset\ &

    Clear\ are both high unless Q was low to begin with. There is one other way to guarantee that Q= low, which is to have the

    Preset\ & Clr\ inputs = Hi, then have the J= Low & K= Hi, then clock the JK (low-to-hi-to-lo). It is CRITICAL that you

    understand that the J & K Inputs and even the Preset\ & Clr\ inputs must be set and stable at least a minimum of 20 to 25

    nSec prior to the clock input going Low, but they can be synchronous with the Clk going Hi. If your simulation has the J or K

    input changing at the same instant as the Clock is transitioned to a Low, this is likely your problem. And if you are pulsing

    the Preset\ or Clr\ low, it must be at least 20 nSec long before returning to a Hi state. Once you have properly preset the JK to a Q=0 state, it should work fine with the clock speed you are using as long as you obey the J & K remaining stable 20 nSec minimum before the Clk goes low. I would recommend that you read the linked datasheet very carefully, especially pages: 1, 5, & 6. I hope this helps. Good luck.

    Kamran Kazem