JFET preamp question

Discussion in 'General Electronics Chat' started by asdiasx, Oct 18, 2012.

  1. asdiasx

    Thread Starter New Member

    Oct 18, 2012
    I've seen some preamp projects with n-channel JFET (audio preamp) were I could not understand the biasing process.

    By the books the VGS needs to be negative related to the source to set a quiescent point.

    But on these projects the source is linked directly to Ground (no RS) and the gate is also linked to ground by a resistor (RG).

    With this config both (Gate and Source) should be at 0V, so how this operates without distortion??? Mainly during the positive cycle of the input signal....

    I'm attaching the link for a circuit sample:


    Thanks in advance!
  2. blah2222

    Distinguished Member

    May 3, 2010
    The JFET will still operate with Vgs = 0 as it is a depletion-mode transistor. It will turn off with anything more negative than around -3 V. Theoretically at Vgs = 0, this will provide Id = Idss (max current) but wont be that stable.

    Check out this thread I posted a while ago for more info.

    asdiasx likes this.
  3. Audioguru


    Dec 20, 2007
    Simply look at the datasheet for the Japanese 2SK170 Jfet. It comes pre-tested into 3 groups of IDSS:
    Grey= 2.6 to 6.5mA
    Blue= 6 to 12mA
    Violet= 10 to 20mA.

    Since the drain resistor is 2400 ohms and the supply is 24V then the Jfet is saturated and will not work if its IDSS is 10mA or more. So pick a grey one.
    asdiasx likes this.
  4. asdiasx

    Thread Starter New Member

    Oct 18, 2012
    Thank you guys for the help!;)

    But I still have a doubt, as the source will always be at 0V (in the example), and the gate is not receiving any biasing voltage, it will will be also 0V when there is no input signal. With this scenario, the current would equal Idss but will be "limited" by the Drain resistor. Ok?

    My questions are:
    1- When an audio signal is applied at the input (AC only), there will be negative cycles, that will decrease Id, correct?
    2- At the positive cycle of the sinusoid the gate will become positive. How will the Id change if the maximum value should already be reached with 0V?

    Sorry if I'm not clear as english is not my native language, but I'd really appreciate your help to make me understand the theory behind this...


    Adriano Dias
  5. Ron H

    AAC Fanatic!

    Apr 14, 2005
    Idss is NOT the maximum drain current. If Vgs goes positive, Id will be greater than Idss, unless it is limited by the drain resistor. As Vgs is increased above 0V, gate current will begin to flow. 500 millivolts p-p will probably not cause significant gate current to flow. 1V p-p will cause a little bias shift. You will not see signal voltages this large from a microphone or pickup.
    If the input is cap-coupled, gate current will charge the cap slightly on the largest positive signal peaks, forcing the DC gate bias to go below zero volts. In this sense, it is self-biasing to an extent. As I said, this would be an unusual situation.
    asdiasx likes this.
  6. asdiasx

    Thread Starter New Member

    Oct 18, 2012
    Thank you Ron! You got what I was missing...

    I was researching the net for JFET Biasing and saw some pages saying that the gate should NEVER be positive (on N Channels)... This messed up my mind trying to understand...

    But now I guess that when the signal is small enough and once, as you clarified, the Id can be higher than Idss, I can understand how the circuit works!! :D

    It's a pity we don't have some graphics on the datasheets with the Id behavior with small positive gate biasing...

    Thank you all!

    Adriano Dias