IVC102 Transimpedance Amplifier Help

Discussion in 'The Projects Forum' started by blah2222, Jul 10, 2011.

  1. blah2222

    Thread Starter Well-Known Member

    May 3, 2010
    Hello, I am undertaking a project where I am to eventually have a real-time measurement of current from a biosensor. The levels of current are in the 10's of nano- to a couple picoAmps.

    I decided to check out the Burr Brown IVC102 datasheet and start figuring out how this transimpedance amplifier works.

    I understand it's premise, instead of using a large valued resistor in the gigaOhms to provide a high gain, an integrating capacitor is used over an integrating period to provide high gain. That part makes sense to me, but when they go over the actual application of the chip, I start to get confused.

    If you go down to the SWITCHED-INPUT MEASUREMENT TECHNIQUE section, it goes through the different rest/set periods of the switches involved. The Rest Period makes sense, in that Vo is tied to ground, through S2 being closed, and S1 being open, so whatever charge Cint had stored on it would be discharged through to ground. The Pre-Integration Hold then opens S2, (with S1 still open), causing the capacitor's voltage (Vo), to be held constant, floating at 0 V. It says that at this time an A/D measurement can be read, but it will always be 0 V... What is the use in reading that?

    Also... Dumb question, but in this model the current source has a parallel resistance and capacitance and they say that the source capacitance is charging while S1 is open. If this current source from my sensor is just a randomly fluctuating value and there is a current path through the resistor, how is this source capacitor being charged?

    From here it moves onto the Integration Period when S1 is closed and S2 is still open. It says that the charged stored on Csource is passed to the Cint... Isn't the current source now just allowed to pass it's charge to Cint, nothing to do with Csource? And then finally the Hold Period, where S1 is opened and causes Vo to float (Cint charged). Should THIS be when an A/D measurement is read because it is the voltage that is desired (an integrated current)?

    Hopefully that made some sense and my questions were reasonable. Thanks a lot!

  2. MrChips


    Oct 2, 2009

    If you check the magnified window in Figure 1b and read the data sheet you will see that there is still some offset voltage on reset = Vos + Iin x Rs2. This "zero" voltage should be measured and subtracted from the final reading.

    The R and C in Figure 3 is just their way of modelling the photodiode. You can just ignore these for this discussion.

    Just follow the timing requirements for S1 and S2 as shown in Figure 3.

    Note that you will need a stable timebase since the output is proportional to the integrating interval. This period must be held absolutely constant for accurate readings.

    This is an integrating amplifier and typically you will be using an integrating time of 16.667ms to reject line frequency noise. Don't expect high sampling rates.
    Last edited: Jul 10, 2011
    blah2222 likes this.
  3. blah2222

    Thread Starter Well-Known Member

    May 3, 2010
    Okay gotcha, that makes a lot more sense now.

    One thing though, the datasheet says that an advantage of the Switched-Input Integration Technique over the Basic Reset-Integrate Technique is that it allows for continuous integration.

    I mean, can't you say that for both techniques as well? The simple case just resets->integrates->resets->... while the complex case just resets->holds->integrates->holds->resets->...

    How is that even continuous anyway?