issue with single ended to differential output op amp circuit

Thread Starter

Gibson486

Joined Jul 20, 2012
344
I am trying to convert a single ended waveform from an stm32 mcu to a differential one. The first issue was with the the non inverted signal. When I disable the buffer, it limits the output to 1V (when it should be 3.3V). When I enable the buffer, the issue goes away and I get the full swing. Perhaps the DAC has high output impedance and forms a divider with my pull down? The next issue is when I get the full swing from the noninverting op amp, the inverting op amp now outputs no more than -1V. I am more confused about the 2nd issue. Any ideas?

My rails are 5 to -5.
The op amp is a dual op amp opa2172.
The signal is something close to a sine wave.
Schematic is attached.

MOD:Cleaned up your image.E

op amp.png
 
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Thread Starter

Gibson486

Joined Jul 20, 2012
344
Seems like I did actually as I should....

My equations get simplified a lot since since I have a dual supply and my reference is ground...
 

Audioguru

Joined Dec 20, 2007
11,248
Doesn't the DAC have a DC output that is modulated by the AC? But your opamps are DC-coupled and the DC is affecting them. Simply use an input coupling capacitor.

Your resistor values seem very low. Try 100k instead of 10k.
 

Thread Starter

Gibson486

Joined Jul 20, 2012
344
Fixed it.

1. Changed the resistor values to 100K. That made the inverting side better.
2. Realized there were clamping diodes at the output (dope!!!!). Took those diodes off, viola! What is weird, though is that those diodes are rated to 5.5V. not sure why it clipped so early.

In the end, I had to ac couple it and change it so it spanned from -5V to +5V on both signals (before, it was 0V-5V on one signal and -5V-0V on the other).

My last issue now is that the transitions from the DAC are noticeable. I normally would not care, but in the op amps, those transitions turn in to oscillations. On the inverting side, it gets worse and it looks like real spikes. I am guessing that is just the small signal response. hoe do you overcome that?

first stage:
upload_2019-2-6_9-6-46.png

2nd Stage
upload_2019-2-6_9-10-18.png
 
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