Hey everyone, I put the values of the following into the circuit and I do not get what is expected.

A B
1 1
1 0
0 1


When I put the values, manually, into the circuit, I get the following results:

A B A>B A=B A<B
1 0 0 0 0
1 1 1 1 1
0 1 0 0 0

This is incorrect. Could someone else give the circuit a go to see if you get the same values as me?
Thanks!

 

The circuit appears to be correct.

 

Ok, I will explain what I am doing so you can guide me on what I am doing wrong. I am putting in the value A = 1, B = 0. The diagram below shows my steps.

 

Remember, these are NAND gates.

 

Ah, now I see my mistake. Thanks alot MrChips! If you don't mind, I also have another question. The truth table for the 1 bit magnitude comparator would look like:

A B A>B A=B A<B
0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0

So my equations would be:
F1(A>B) = AB'
F2(A=B) = A'B' + AB
F3(A<B) = A'B

How would this lead me to the schematic attached?

 

Are you sure that you understand the truth table of a NAND gate? http://en.wikipedia.org/wiki/Negated_AND_gate

I see some errors in the manual simulation. Take a look at the diagram below and identify the differences between it and yours. Then complete the simulation by replacing the question marks with their logic values...

 

@djsfantasi, yes i messed up with the NAND, I understand it now. Could either of you help me with my second question, which is how to go from the truth table to the scematic?

Thanks for helping also!

 

That is bit trickier. I can see how you can arrive at the solution knowing the solution ahead of time but I cannot arrive at the circuit from the equations.

The first example:

F1(A>B) = AB' = ( (AB')' )'

but the circuit uses (AB)' instead of just B'. The A in this gate is redundant.

 

Ok let me pose a different question. From the boolean equations derived above, they all contain NOT gates. My schematic can only have NAND gates. I am not bothered about obtaining the 1 bit comparator NAND schematic as shown above, just so that it contains only NAND gates.

Also, F1, F2 and F3 are all separate. How would three functions be combined into one, on a boolean equation level?

 

I know so far no other way than just looking and tweaking the expressions' terms until you find some common ones that are shared among them.

If someone else knows a better way, I 'd like to hear it too.

 

That's a shame. Actually want I am asked to do is implement a 2 bit comparator using only NAND gates, making it even worse to tweak!

 

I didn't initially reply, because I would use a brute force method.

NAND gates are considered universal, as all other gates can be contructed from them. The Wikipedia article shows that well. By combining your three functions, visually, I can see how to develop the circuit - but I am only a hobbyist and cannot explain my methods.

(a NOT gate is a NAND gate with it's two inputs tied together)

 

All posts help. I guess the brute force approach is the way forward!

 

Why don't you take a look in this thread too: http://forum.allaboutcircuits.com/showthread.php?t=60610&highlight=NAND+gate

 

OK, this really intrigued me. I kept working on it.

First, I noted that the truth table for F2(A,B) is the same as an XNOR gate.

The NAND gate equivalent for this gate is as follows is easy to find. So this implements F2.

F1 and F3 are similar in form, A'B versus AB'... Let's look at the latter first, F1(A,B)=AB'. If you look at the XNOR gate equivalent, you might find a place to use as an AND gate with the addition of one more gate. But how do we get B'?

This is where a little trick comes into play. Examine the circuit carefully. If A=0, then F1() will always be 0. But if A = 1, then the NAND gate marked with an 'a' will act as a NOT gate for the B signal, giving us AB' ! So F1() is almost implemented already within the XNOR circuit.

The same trick applies to F3() and A'B...

Try and work it out yourself.

 

Which actually makes perfect sense, because the XNOR's expression is AB'+A'B.

But all in all, it was a beautiful trick using one gate for both complements.

 

Well done djsfantasi, I'm impressed! Thanks for everyones input for helping me understand the above!

 

By the way, another way of identifying the trick is to also remember there are two ways of using a NAND gate as a NOT gate. It is the second form which is useful in these cases.

 

nice input you guys!