Is it necessary to maintain Vds > Vgs always???

Discussion in 'The Projects Forum' started by onlyvinod56, Jul 10, 2009.

  1. onlyvinod56

    Thread Starter Senior Member

    Oct 14, 2008
    hello all,
    Before going to test my three phase inverter with a 400VDC...... i want to test it with 9VDC. The gate pulses are of 12VDC magnitude coming out from a IR2110 (high & low side driver). The pulse sequence fashion is correct in oscilloscope....... but both the mosfets in a leg are conducting simultaneously.....
    is there any rule to have vgs < Vds?
    see the attachment

    AAC Fanatic!

    Jul 1, 2008
    I don't think you have your load connected properly. It should be connected between the top Fet's Source and the bottom Fet's Drain. Your 9V supply should be connected between the top Fet's Drain and ground. Have you looked at the IR2110.pdf? It shows a typical hookup.

    There may be other errors that I missed.