IR2184 pinout

Thread Starter

Coucou80

Joined Apr 7, 2018
56
I’m a little confused.
I’ve seen a few schematics online with the ir2184.
Can anybody confirm pin1 on IR2184?
I see sometime as Vcc but on the datasheet i see IN … I’m confused on the pinout.
 

Thread Starter

Coucou80

Joined Apr 7, 2018
56
Thanks for confirming what I thought.
So I’m trying to stimulate this IC through the use of a function generator. I understand that the logic input will go to the IN pin, but what about the negative lead coming out of the function generator? I guess I clamp it to COM ?
Thank you for your answers
 

Thread Starter

Coucou80

Joined Apr 7, 2018
56
On that same topic, I just finished the layout for the IR2184 in a push-pull configuration. Before installing the MOSFET, I checked for gate driving and I was able to see the desired pulse at each of the gate.
Here is my problem:
As soon as I place the transitors in place, the clean gate signal I was having disapears. Drain and Sourse signal is weird also.
Question:
Do I have to place the pulse transformer in order for the gate signal to work? Or should I be able to see my gate-drain-source signal when no load/inductance is applied between drains?
Thanks again for the assistance.
 

Thread Starter

Coucou80

Joined Apr 7, 2018
56
As requested… I appologies for my mess.
This is how the circuit is right now.
Like I said without the FET, the signal is good on LO and HO. As soon as I put the FET in the signal is arbitrary and messy.
Thank you for the assitance.
image.jpg
 
Last edited:

Alec_t

Joined Sep 17, 2013
13,157
What are the two FET drains connected to?
The SD input pin should be connected to Vcc unless the pin has an internal pull-up inside the IC.
10k seems very high for a gate resistor.
Unless the source of the upper FET is being pulsed high I don't see how the 100n boost capacitor can do its job.

Edit:
With Vcc=20V, HO and LO will both be about 20V. That is likely the absolute maximum gate voltage for most MOSFETs, so is not recommended. 10-12V should be enough.
The ground pin of the function generator should connect to the ground pin of the IC.
 
Last edited:

Thread Starter

Coucou80

Joined Apr 7, 2018
56
Thank you for your assistance.
Right now the drains are connected to nothing and thats why my question. Does the drains need to be connected to a load for me to see the transistors gate signal on oscilloscope?

Why when the transitors are not connected I can clearly see the signal at pin LOand HO ?
As soon as solder in the transistor the gate signal is disapear. Is this a normal behaviour?
 

Thread Starter

Coucou80

Joined Apr 7, 2018
56
Just checked the continuity between gate source and its open (no short).
On the board between gate-source its open as well.image.jpg
 

Thread Starter

Coucou80

Joined Apr 7, 2018
56
Yes you read correctly. COM is connected to the 100nF cap in my drawing. I’ll investigate why I did that.
For the two mosfet. The circuit I’m building will be in s push-pull configuration, where eventualy the center tap of a pulse transformer will be connected to a choke, then to Vcc. The two other end of the primary coil of the transformer will be connected to the mosfet drain. Shouldn’t the two source connected to ground also ?
 

Alec_t

Joined Sep 17, 2013
13,157
The 100n cap is not necessary, but simulation with LTspice suggests that the diode from Vcc to Vb is needed nevertheless.
SarahMCML is perhaps thinking the FETs are in the standard half-bridge drive configuration, rather than a push-pull configuration?
Shouldn’t the two source connected to ground also ?
Yes, for push-pull operation.
 

Thread Starter

Coucou80

Joined Apr 7, 2018
56
@Alec_t Yes it will be in push-pull config.
I will remove the 100nF cap and try removing the ground link connected to Vs. Not sure why I did that…

Edit: In fact yes Vs has to be connected to ground in push-pull… so I’m still in the trouble shooting mode. I will start with the resistors
 

Thread Starter

Coucou80

Joined Apr 7, 2018
56
All,
Solved!
Issue was with resistor too high at the gate.
Replaced them with 10ohms and all is good now.
Thanks all for the help.
Here is a screenshot at the low side FET drain.
Best regards.
image.jpg
 

sarahMCML

Joined May 11, 2019
168
The 100n cap is not necessary, but simulation with LTspice suggests that the diode from Vcc to Vb is needed nevertheless.
SarahMCML is perhaps thinking the FETs are in the standard half-bridge drive configuration, rather than a push-pull configuration?

Yes, for push-pull operation.
You are absolutely correct! I've been so absorbed with H-bridge drivers for the last few weeks that I totally missed the fact that the lower MOSFET was upside down.
 

Thread Starter

Coucou80

Joined Apr 7, 2018
56
One thing I can recommand is that the use of the electrolitic capacitor between COM and Vcc helps in stabilising the signal at the gates. It will work without it, but it helps significantly in havin a clean signal.
 
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