praondevou
- Joined Jul 9, 2011
- 2,942
Yes. Thanks. This will help when analyzing the logic part.Did that address the question you asked?
Yes. Thanks. This will help when analyzing the logic part.Did that address the question you asked?
Ron thank, like I've been saying this is all new to me. I don't know the ins and outs of this stuff. I was meaning it to be the output/source voltage and input of the IRS2183. Sorry for the confusion.You probably think I am anal, but your timing diagram does not agree with your schematic. See the first attachment. I realize you have the Q number designations on the same line, but those are not unambiguous, because they could refer to source or drain voltage or current, or gate voltage (which I now assume is what you were intending). I think you will agree that showing HIN and /LIN tied together on your schematic, and showing them as opposite polarity on the timing diagram, is potentially confusing to anyone who is not you.
I took the liberty of relabeling your timing diagram so that it is unambiguous, and hopefully is what you intended. See second attachment.
Doing that would put the PWM on all of the logic outputs, wouldn't it?Let's say RON is right and PWM is half of OSC.
The FF inside the 3525 and the 74HC74 are not related even though they come from the same oscillator frequency.
That means you can not be sure that the rising edge at Q of the 74hc74 coincides with the rising edge of the corresponding PWM signal.
Why not use the 74HC74 in your drawing but tie it's D and CL to GND. Then use PWM A to reset it and PWM B to set it. Q would go to U1A and /Q to U1B.
PWM A = High resets the FF and charges Bank B.
PWM B = High sets the FF and charges Bank A.
I can make a drawing later.
Not the way I thought. I still believe that you cannot guarantee that PWM will match the 74HC74 output, and this is what you need for the AND gate, right?Doing that would put the PWM on all of the logic outputs, wouldn't it?
Jony, you measured this on a SG3525? Can you also measure PWM vs OSC?I use my O-scope to capture voltage across Ct capacitor and two outputs.
Yes I can.Jony, you measured this on a SG3525? Can you also measure PWM vs OSC?
The saw tooth vs PWM seems to confirm Ron's drawing.
Ok, I guess I do not understand the requirements.@Praondevou, Won't work like it's supposed to.
1. Each PWM output is only good to ~ 49%.
2. The PWM should be from ~ 5% to 90%. If there would be a disruption in the PWM during the discharge, like the 3525 does to get more than 49% PWM, the spark would stop and not have enough voltage to reionize the gap.
3. The only thing that should be a PWM is the output on Q3, for each cap bank.
4. Cap bank 'A' should be charging when cap bank 'B' is discharging, and vise-versa.
1. Two PWMs that are the same but separate, one for 'A' and one for 'B'. This is what the 'AND' gate after the 74hc74 does in the logic.Ok, I guess I do not understand the requirements.
Let me see if I get this right now. You want:
1. Two PWMs that do not overlap
2. Both can be from 5% to 90%, if one is 5% then the other is 85%
3. you cannot use the 3525 because there is a pause between both PWM, i.e. you cannot just OR them
The UC3842A doesn't have an osc output. How would it be used to drive the 74hc74?Unless you want to go with the 555 solution you could also use a UC3842A which has typically max duty cycle of 96%. Very common model.
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