Does this look about right?

 

Yes, upper and lower transistors form two common half-bridges.

Ok, if Q3 and Q4 are just having opposite gate signals you can tie HIN and /LIN of U2 together. I don't see a problem with that. Makes a variable ON/OFF time for Q3 and Q4. (Within limits).

What about the Comparator logic?

The comparator logic is;

1. when top comp is above 90V, it should be high. If it doesn't get above 90V it would be low and not allow discharge to happen.

2.The latch is to keep the high on the 'and' gate,allowing the discharge to happen. It is a transparent latch and should latch as the mosfet switches on. With out the latch, as the cap voltage falls,due to discharge, the gate would shut down early.

3.If the lower comp falls below 10V at any time in the discharge, it will shut down the 'and' gate turning off the discharge.

 

The comparator logic looks right then.

Which pin of the SG3525 is "FREQ"? Are you using it with an external clock and this is the same as the external clock?
Or is this the internal oscillator?

EDIT: forget it. It's pin 4, I see.

 

I don't know the SG3525 good enough. The oscillator frequency is twice the PWM, right? So the frequency after the 74HC74 would equal PWM. It would only be interesting to know if the phase is always the same.
There is also nothing that tells the 74HC74 where to start after power up. This however you can easiy accomplish with an RC at the RESET/SET input. I'm just not sure about the SG3525.

My question is: Would it be possible having a PWM signal ON while the output of the 74HC74 is inverted (OFF) in an unpredictable manner after each power up?

 

@Praondevou, yes the timing is what I thought I was showing in post #35. But is was calling it charge and discharge.

Thank you for showing me how to identify the various fet's and drivers in a more coherent way. Didn't know how to do it correctly. You are teaching me so, so much, and I really do appreciate it.

You had me panicking about the comparators. I spent time figuring out what I thought was the way to do it, and when you said it was wrong... I'm glad it wasn't.

I used the SG3525 in a DC speed control. To me it is easier than a 555 and lm339 to do PWM. As long as you use the PWM out put to drive fet gate drivers it works great. Still don't understand why people want to not use gate drivers? makes life a lot easier.

 

I don't know the SG3525 good enough. The oscillator frequency is twice the PWM, right? So the frequency after the 74HC74 would equal PWM. It would only be interesting to know if the phase is always the same.
There is also nothing that tells the 74HC74 where to start after power up. This however you can easiy accomplish with an RC at the RESET/SET input. I'm just not sure about the SG3525.

My question is: Would it be possible having a PWM signal ON while the output of the 74HC74 is inverted (OFF) in an unpredictable manner after each power up?

My understanding of the SG3525 family, there are other names for same chip depending on maker, is that the clock and PWM frequency are one and the same. It is like a 555 and lm339 in one chip. But also has other options built in, shut down, over current, etc.

Since the PWM is sent to both 74hc21 gates, which ever, Q or /Q is high, it doesn't matter. As far as I can see. As long as the other conditions for the logic are met. And if it takes a few clock cycles for the comparators to go high (for the caps to get to voltage needed) it won't make a difference.

I'll draw up a new timing diagram using the Q1, Q2, Q3, Q4, U1, U2, designations for both cap banks.

 

This guy writes exactly what I was thinking. According to him PWM is half of oscillator output.
Since you want to use both signals I would first make sure how exactly they are related. Before continuing with your circuit development.

I would just setup a 3525 for a quick test. Unfortunately I don't have one...

 

In the SG3525 data sheet it, I think, addresses this. Each PWM output is capable of up to 45% duty cycle. You need to connect both outputs by a diode 'OR' to get up to 90%. And by doing this the frequency and PWM are pulse by pulse, not alternating pulses or 1/2 of the frequency. Or at least that's how I understand it, could be wrong.

If not I will resort to using a 555 and 339 for PWM.

 

OK, new timing diagram and schematic time. I think I have correct this time. Both cap banks, 'A' and 'B' are shown this time. And the timing for each of the switching components.

 

OK, new timing diagram and schematic time. I think I have correct this time. Both cap banks, 'A' and 'B' are shown this time. And the timing for each of the switching components.

Don't Hin and /Lin need to be identical? The inversions required to drive Q2 and Q4 happen inside the IRS2183.

 

Ron, they are identical, but inverted. Q1 and Q2 are driven by U1 making a half bridge. Q3 and Q4 are driven by U2 making a half bridge.

The way the logic is done, Q1 & Q2 are high twice as long as Q3 & Q4.

 

Ron, the are identical, but inverted. Q1 and Q2 are driven by U1 making a half bridge. Q3 and Q4 are driven by U2 making a half bridge.

The way the logic is done, Q1 & Q2 are high twice as long as Q3 & Q4.

If you want the LO and HO outputs to be complementary, then HIN and /LIN must be identical (connected together). That's what this thread was originally about!

 

Ron, I'm missing some thing here? The individual half bridges are complimentary. When U1 Hin is high /Lin is low. When U1 Hin is low, /Lin is high. The same for U2.

But there are two different IRS2183 chips. Each is controlled by a separate signal from the logic circuit. So as the timing diagram shows Q1 & Q2are compliments, Also Q3 & Q4 are compliments.

I don't know any other way of showing it. Or I'm missing your point.

 

Ron, I'm missing some thing here? The individual half bridges are complimentary. When U1 Hin is high /Lin is low. When U1 Hin is low, /Lin is high. The same for U2.

But there are two different IRS2183 chips. Each is controlled by a separate signal from the logic circuit. So as the timing diagram shows Q1 & Q2are compliments, Also Q3 & Q4 are compliments.

I don't know any other way of showing it. Or I'm missing your point.

You are missing my point. Read post #8 again. Condition #3 in that post is what you have drawn in your timing diagram.
In order to have Q1 and Q2 turn on alternately, HIN has to be identical to /LIN.

 

Ron let me think on this, and try to figure it out. This is all new to me. I will return.

 

Ron let me think on this, and try to figure it out. This is all new to me. I will return.

Have you forgotten that this was the original topic of this thread? From your post #12:

My reason for wanting to use this chip is eliminating the use of an inverter chip in my logic circuit.

I'm assuming you meant that you wanted to be able to drive HIN and /LIN with the same signal. Well, you can!
This is because, internal to the chip, LIN gets inverted before it shows up at LO. Hence the inversion bar over LIN (or, here on the forum, the / in front of LIN). This signifies that it is active low, i.e., when the input is low, the output is high.

 

And I have shown that in my schematics. Right at each IRS2183 the pins are connected together. I'm including drawings that are color coded showing the logic circuit, switching circuit and timing diagram.

The whole reason I started this thread was to find out ;
1. if the drivers worked the way they do.
2. to find out if using them would work to recharge the boot caps. Since the principle fets Q1 and Q3 are in a high side configuration.

 

And I have shown that in my schematics. Right at each IRS2183 the pins are connected together. I'm including drawings that are color coded showing the logic circuit, switching circuit and timing diagram.

The whole reason I started this thread was to find out ;
1. if the drivers worked the way they do.
2. to find out if using them would work to recharge the boot caps. Since the principle fets Q1 and Q3 are in a high side configuration.

You probably think I am anal, but your timing diagram does not agree with your schematic. See the first attachment. I realize you have the Q number designations on the same line, but those are not unambiguous, because they could refer to source or drain voltage or current, or gate voltage (which I now assume is what you were intending). I think you will agree that showing HIN and /LIN tied together on your schematic, and showing them as opposite polarity on the timing diagram, is potentially confusing to anyone who is not you.
I took the liberty of relabeling your timing diagram so that it is unambiguous, and hopefully is what you intended. See second attachment.

 

RON, did you find any info on how exactly PWM outputs and oscillator frequency are related? I can't find a timing diagram for the 3525.
In order to check the logic circuit one need to be sure what comes out of the 3525.

 

RON, did you find any info on how exactly PWM outputs and oscillator frequency are related? I can't find a timing diagram for the 3525.
In order to check the logic circuit one need to be sure what comes out of the 3525.

After studying the block diagram and the schematics in the datasheet, I am pretty sure that PWM output A and PWM output B are each at half the oscillator frequency, and alternate with each other.
Did that address the question you asked?
Unfortunately, I haven't been following that part of the thread, so I don't know what the implications are.