Interrupts latency

Thread Starter


Joined Jan 6, 2004
Micro 18F452

I have implemented a clock, with the module CCP1 (compare mode) against TMR1 (counter mode).

To get a fixed duty cycle in RC2 pin, upon matching TMR1, the ISR loads alternatively two values in the CCPR1H:L registers.

Above ISR is high priority. Another one, running in low priority have no problems to coexist.

Regarding the latency, in the manual, I read:

For external interrupt events, such as the INT pins or the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles.

The exact latency is the same for one or two-cycle instructions.

Having run all this through MPSIM I found a variation in the time elapsed between successives entries to the ISR, with the adequate allowance for the actual value loaded in the CCPR1 registers which seems to be of 1 or 2 Tcy.

My questions:

a) The paragraph in bold, is it actualy including the rest of the interrupts as well? Found it quite unclear.

b) Is it any way to compensate the differences in time elapsed between succesive entries to the ISR?

Help appreciated.


Joined Oct 14, 2005
a. I should think so. The latency is independent of one or two cycle instructions whether the trigger is internal or external. The reason external interrupt events having different latencies is because the events are asynchronous to the clock and the latencies depend on which point in time the events occurred and therefore sampled. For internal events, all of them are synchronous to the clock, which should result in fixed latencies.

b. For external interrupt events, I couldn't think of an easy one. It's probably possible with an output pin and a comparator or two. There shouldn't be any difference in latency for internal interrupt events.

If you were referring to internal latency difference, could you elaborate more on your setup/code/sim?

Thread Starter


Joined Jan 6, 2004
The point is: evrything except the restarting of TMR1 is inside the ISR what makes it subject to latency effects. And that's what I want to escape from.


Joined Jan 28, 2005
From what you have indicated, it sounds like the ISR contains the bulk of the code in the program.

As a rule, the code inside an ISR is kept as spartan as possible as a means of preventing any problems with interrupt latency.

It would be helpful if you could post a copy of your source code.



Joined Oct 14, 2005
I take it that you are experiencing different latencies for the same internal interrupt event. is this right? If so, I think it would be better if you post your code and we can have a look.

Thread Starter


Joined Jan 6, 2004
Found the solution.

Gracias for all your help and your time!

Rich (BB code):
   ;009 ISR HIGH.ASM
;High priority interrupts service routine
;Interrupts desabled. STATUS, W & BSR saved automatically in the fast stack.
;actual interrupts service code starts here
    RLNCF TMR1L,W           ;make W =PC offset =(value of TMR1L *2)
    ADDWF PCL,F             ;springboard ready
    NOP                     ;pontoons
    NOP                     ;for the
    NOP                     ;PC to
    NOP                     ;land
    NOP                     ;HERE (4)
    NOP                     ;or HERE (5)
    BTG PIN_CLK             ;toggle pin to materialize the clock
    ;let's load the oposite value of HALF_T to CCP1
    BTFSS LOAD_HALF_T1      ;=1, must load...
    BRA LOAD_HALF_T2_VALUES ;=0, load HALF_T2 values to CCP1
    MOVFF HALF_T1_H,CCPR1H  ;... HALF_T1 values
    MOVFF HALF_T1_L,CCPR1L  ;loaded to CCP1 registers.
    BTG LOAD_HALF_T1        ;next time will load the other HALF_Tx value
    BCF PIR1,CCP1IF         ;=0 clears CCP1 compare match interrupt flag
    RETFIE FAST             
;STATUS, W & BSR retrieved from the fast stack. Back to main line code
;with interrupts enabled.
    MOVFF HALF_T2_H,CCPR1H  ;HALF_T2 values
    MOVFF HALF_T2_L,CCPR1L  ;loaded to CCP1 registers.
;actual interrup service code ends here
Simple, isn't it?