# Input offset current/voltage

#### mentaaal

Joined Oct 17, 2005
451
Hey guys, i am trying to find the difference between input offset current and input offset voltage in opamps...

In the art of electronics it says:
Input offset current is a fancy name for
the difference in input currents between
the two inputs. Unlike input bias current,
Input current the offset current, I,,, is a result of man-
ufacturing variations, since an op-amp's
symmetrical input circuit would otherwise
result in identical bias currents at the two
inputs. The significance is that even when
it is driven by identical source impedances,
the op-amp will see unequal voltage drops
and hence a difference voltage between its
inputs. You will see shortly how this influences
design.
Which seems to suggest the two are the same thing or at least related.. But in my notes my lecturer treats them as two distinct errors as he eventually adds the errors together?

#### mik3

Joined Feb 4, 2008
4,843
Lets call the inverting input as 1 and the non-inverting input as 2.

The bias current is defined as Ibias=(I1+I2)/2 (1)

The offset current is defined as Ioff=I1-I2 (2)

If you combine the two above equations you will find that:

I1=Ibias+Ioff/2 (3)

I2=Ibias-Ioff/2 (4)

These is the equations which relate this quantities. Now, by bias current we mean the input current the transistor (internal transistor of the input differential stage) needs to produce an amount of output voltage. On datasheets you find the average bias current (equation 1) of the two inputs. If you want to calculate the actual bias current of each input you have to use equations 3 and 4. Now, the offset current which appears in the equations is due to the fact that the input transistors (internal) does not have exactly the same gain and each one draws a bit different amount of current. The difference between these two input currents is called the offset current (equation 2). Your teacher is right because the error voltages created by the slight different bias currents of each input are not the same as the offset voltage. The offset voltage is an internal voltage created on the output of the differential input stage because the gain of the transistors are not exactly matched (gain - base-emitter diode not the same). You can treat this offset voltage as a DC voltage on one of the inputs off the amplifier (depends). Because the offset voltage (DC source on the input) and the offset voltage created by the offset current are in series you can add them together to get the total error voltage.

#### mentaaal

Joined Oct 17, 2005
451
That was a such an informative reply i am actually going to keep that in my notes!

Thanks for going to the trouble. It is not going to get wasted. I will be using that for our next asessment

#### mik3

Joined Feb 4, 2008
4,843
I am happy my information are useful to you #### mentaaal

Joined Oct 17, 2005
451
Opamps are the devil, i have spent so, so many hours trying to understand them!

In an opamp question we are given:

Iio = 10nA
Ib = 50nA
Vos = 2mV
gain = 10
Aol = 100dB
Rf = 10k (negative feedback resistor)
In working out the steady state errors: Vos just gets added to Rf*10nA = 2.1mV which later gets added to the gain error factor for a total error.

Whats bother me here is that the art of circuits refers to Vos as:
The difference in input
voltages necessary to bring the output
to zero is called the input offset voltage
V, (it's as if there were a battery of that
voltage in series with one of the inputs).
Then by this definition doesnt that make Vos an input error that still has to be amplified by the opamp? Why do we just assume that this means that there will be an extra 2mV at the output?

Another thing i am confused about is in the calculation of the steady state errors in an integrator.

Vout is defined to be: -1/RC∫Vin dt ± 1/c∫Ib dt ± 1/RC ∫Vio dt + Vio

Ok before I go nuts:
Why is the bias current only 1/c∫Ib dt and not 1/Rc∫Ib dt?
And the same question as the first one: why is vio dealt with as: 1/RC ∫Vio + Vio??

#### mik3

Joined Feb 4, 2008
4,843
Whats bother me here is that the art of circuits refers to Vos as:

Then by this definition doesnt that make Vos an input error that still has to be amplified by the opamp? Why do we just assume that this means that there will be an extra 2mV at the output?
No, this is an error which has to be added to the other errors because the offset voltage exists internally. The art of the circuits just says a way to minimize this offset voltage by adding a voltage source between one of the inputs and the relative input resistor. The polarity of the voltage source depends on the internal offset voltage polarity. Imagine that you have an ideal op amp (without errors), to create this offset voltage error you add a voltage source (with its voltage equal the offset voltage) between one of the inputs and the relative input resistor. To eliminate this offset voltage (voltage source) you have to put another voltage source in series with it and with opposite polarity. Thus this another voltage source is has an equal voltage (magnitude) to the offset voltage and is that the art of circuits mentions.

#### mentaaal

Joined Oct 17, 2005
451
Thanks for that Mike. What i am still confused about is, if this is only an error in the output voltage, why did my lecturer, for the integrator, integrate this error as well? ( 1/RC∫Vio dt) If you have to do this, do you not have to do something similar with Vos for ordinary resistance inverting opamps?

#### mik3

Joined Feb 4, 2008
4,843
Yes sure, you have to add the errors on the output voltage in all cases of operation of the op amp.

#### mentaaal

Joined Oct 17, 2005
451
ARGGGHHh then why didnt my lecturer say so! Its so hard to study my notes lemme tell you!

Ok well then what up with the dealing of the bias current? Why does it not take into account Rin? (for first example - the output error was Rf*Iio and for the integrator : -1/C∫Ib )

And my lecturer seems to have omitted Iio for the integrator... is that intentional or perhaps just a mistake do you think?

#### mik3

Joined Feb 4, 2008
4,843
Well, i am not sure because i havent analyzed an integrator in such depth until now to know how the offset current affects it but i believe he just omitted it for simplicity. The depth of analysis depends on how accurate you want your circuit to be. If you want a very accurate analysis you have to take into account that the values of the resistors, for example, vary with temperature and have tolerance and so on.......
In electronics you dont have to design every time the perfect design, you design with the accuracy your application needs. Remember, the greater accuracy and performance of any circuit the greater the cost of the design and manufacture.

#### mentaaal

Joined Oct 17, 2005
451
Well believe me mike, i have absolutely no intention of designing anything at the moment... I am just one of those people that, cannot tolerate not understanding my notes.

I just want to understand whats going on here thats all...

Which reminds me, you might wanna take a look at this little funny:
http://xkcd.com/356/

Thanks for your help though, tis greatly apprectiated.

#### mik3

Joined Feb 4, 2008
4,843
I am sorry but i am studying at the moment my university lectures so i cant analyze it for you. Maybe another time i will post what you want to know.

#### mentaaal

Joined Oct 17, 2005
451
No problem, its a forum, not an IM and I expect nothing from anyone ;-)

Although i do believe i found the explanation i am looking for. Perhaps it will help you too if you are interested: (interesting part in bold)

10.1.1 Input Bias Current
As briefly noted in Chapter 1, the first stage of an op amp is a differential amplifier.
Figure 10.1 shows a representative circuit that could serve as an op amp input stage.
Clearly, the currents that flow into or out of the inverting (-) and noninverting (+) op
amp terminals are actually base current for the internal transistors. So, for proper
operation, we must always insure that both inputs have a DC path to ground. They
cannot be left floating, and they cannot have series capacitors. These currents are
very small (ideally 0), but may cause undesired effects in some applications.
Figure 10.2 can be used to show the effect of nonideal bias currents. It illustrates
a basic op amp configured as either an inverting or a noninverting amplifier
with the input signal removed (i.e., input shorted to ground). The direction of current
flow for the bias currents and the resulting output voltage polarities are
essentially arbitrary, since different op amps have different directions of current
flow. However, for a given op amp, both currents will flow in the same direction
383
384 NONIDEAL OP AMP CHARACTERISTICS
FIGURE 10.1 A representative input
stage for a bipolar op amp.
FIGURE 10.2 A model that can be
used to determine the effects of bias
current.
(i.e., either in or out). For our immediate purposes, let us assume that the arrows
on the current sources indicate the direction of electron flow. We will now apply
Ohm's Law in conjunction with the Superposition Theorem to determine the output
voltage produced by the bias currents. First, the noninverting bias current
(with the inverting bias current set to 0) will cause a voltage drop across RB with a
value of
Nonideal DC Characteristics 385
This voltage will be amplified by the noninverting gain of the amplifier and
appear in the output as
It should be noted that this voltage will be negative in our present example, since
we assume that the electron flow was out of the input terminals.
Now let us consider the effect of the bias current for the inverting input
According to the Superposition Theorem, we must set the bias current on the noninverting
input to 0. Having done this, we see that since no current is flowing
through RB there will be no voltage across it. Therefore, the voltage on the {+)
input will be truly 0 or ground. Additionally, we know that the closed-loop action
of the amplifier will force the inverting pin to be at a similar potential. This means
that the inverting pin is also at ground potential; recall that we referred to this
point as a virtual ground. In any case, with 0 volts across Rj there can be no current
flow through R/. The entire bias current for the inverting input, then, must flow
through RF (by Kirchhoff's Current Law). Since the left end of RF is grounded and
the right end is connected to the output, the voltage across RF is equal to the output
voltage.
Therefore, the output voltage caused by the bias current on the inverting
pin can be computed as
Since current has been assumed to flow out of the (-) pin, we know that the resulting
output voltage will be positive. Note that this is opposite the polarity of the (+)
input.
Now, continuing with the application of the Superposition Theorem, we
simply combine (algebraically) the individual voltages computed above to determine
the net effect of the two bias currents. Since the polarities of output voltage
caused by the two bias currents are opposite, the net output voltage must be
The manufacturer does not generally provide the individual values of both bias
currents. Rather, the bias current (IB) listed in the specification sheet is actually an
average of the two. In general, the two currents are fairly close in value, so if we
assume that the two currents are equal, the preceding equation becomes

#### mentaaal

Joined Oct 17, 2005
451
Ok, in trying to further understand the effect of bias current in a circuit, i re-read the above quote a couple a million times. Unfortunately, when i copied it, the formulae didnt copy so instead i have uploaded the relevent section here in a pdf form. The author describes the voltage inputs to the circuit as being 0 volts. And using this, he shows how the output voltage depends on Ib*rf. what i dont understand is how this line of thought applies to input voltages that are not 0 volts. The reason why i dont follow this is that he says that when the current going into the non-inverting input is allowed to be zero, the voltage at the inverting terminal will be zero too (virtual ground) and so no current flows through R1. But this does not follow for input voltages != 0... does it?

He clearly shows that it can be done like this as he does in an example in the pdf.

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#### mik3

Joined Feb 4, 2008
4,843
For an ideal op amp the voltage difference between the inputs is zero because it has infinite gain. In a real op amp, because the gain is not infinite, you have a small voltage difference between the inputs but it is still very small assuming the amplifier works in the linear mode. This is true for every voltage and not only for zero. That is the non-inverting input is held at 3 volts for example, the voltage on the inverting input will be very close to 3 volts if the op amp works in its linear region.

#### mentaaal

Joined Oct 17, 2005
451
Analogue circuits is starting to make me feel incredbly stupid.

I agree with what you are saying Mike but my impression of the idea the author is trying to put forward is that on the inverting pin, because the input before R1 is 0 and because of virtual ground, no current flows through R1. Thats all fine and dandy but what if the input before R1 is not 0 volts, then the there would be a voltage difference between the terminals of R1.

#### mik3

Joined Feb 4, 2008
4,843
In reality even with zero volts on the input before R1 a small current flows through R1. But if we assume an ideal op amp then for current to flow through R1 a non zero voltage has to be applied on the input before R1.

#### mentaaal

Joined Oct 17, 2005
451
But if the there is a voltage across R1 then it cant be said that no bias current will flow through R1. Thats the basis of the author's argument, that is because Vin was 0 volts, the bias current would not flow through r1. (both terminals at same potential)

Am i just looking at this wrong or is there another explanation?

Last edited:

#### mik3

Joined Feb 4, 2008
4,843
It can flow through Rf and the output will be slightly negative as to have zero volts on the inverting input.