Hi,
I have P-MOSFET that is used to generate VPP (6V) for microcontroler blow fuse (secure device). Line for VPP is shared with 1.8-3.3V programming clock signal. What is the influence of turned off P-MOSFET (Vg=Vs=4.5-6V) drain connected to logic clock signal (1-8Mhz square, 1.8-3.3V generated by LVC logic family)? I am worried about extra capacitance, but not sure if the right parameter (that I am looking for) in datasheet is Coss. I need P-MOSFET with low Rdson (less than 100mOhm) and with minimum impact on logic clock signal when P-MOSFET is off. Switching characteristic of P-MOSFET is irelevan in my case, only important is MOSFET on state (minimum Rdson, clock signal is off) and MOSFET off state (minimum impact on clock signal).
Regards,
Josip
I have P-MOSFET that is used to generate VPP (6V) for microcontroler blow fuse (secure device). Line for VPP is shared with 1.8-3.3V programming clock signal. What is the influence of turned off P-MOSFET (Vg=Vs=4.5-6V) drain connected to logic clock signal (1-8Mhz square, 1.8-3.3V generated by LVC logic family)? I am worried about extra capacitance, but not sure if the right parameter (that I am looking for) in datasheet is Coss. I need P-MOSFET with low Rdson (less than 100mOhm) and with minimum impact on logic clock signal when P-MOSFET is off. Switching characteristic of P-MOSFET is irelevan in my case, only important is MOSFET on state (minimum Rdson, clock signal is off) and MOSFET off state (minimum impact on clock signal).
Regards,
Josip
Last edited: