improper glitch simulation with orcad pspice

Discussion in 'Electronics Resources' started by dawsontm, Feb 10, 2011.

  1. dawsontm

    Thread Starter New Member

    Feb 10, 2011
    Hi -

    I'm using pspice for 10.3 and the circuit I am simulating at the moment has a 688hc magnitude comparator comparing 8 fixed logic levels to 8 Q outputs from a hc4020 14 stage ripple counter running from a 32.768 KILO hertz clock. The output of the magnitude comparator is being clocked by a 74hc74 FF by the same clock (either phase). Using a same clock or an inverted version of the same clock gives about the same number of errors by PSPICE. These errors are described below.

    The problem is that for a one second simulation, pspice insists on giving thousands of errors, basically one for each glitch at the 688 output and will not properly simulate the flip flop output showing an indeterminate output (neither high nor low) at the Q output of the FF virtually all the time.

    Here is a condensed version of one of the simulation error messages (remember, there are about 10,000 of these for this one simulation):

    PERSISTENT Hazard at time 26.579436ms
    at "DATA" input of X_U21B.UFF1
    Caused By: GLITCH Hazard at time 26.3811404ms
    Device: X_U3.UHC688DLY
    NODEs: X_U3.PEQBAR (IN1) => LOWON25 (OUT1)
    Pulse width is 8.000E-09
    Noise Margin (tpwrt) is 2.000E-09
    Propagation Delay is 3.000E-08

    How is it that PSPICE flags errors for 8 nanosecond glitches (that are inherent to the HC688, btw) when there is a minimum 190 microsecond setup AND hold time (as seen above) for the FF D input for each and every instance? What is the fix for this? - if this is typical of how PSPICE operates for digital modeling, it is not very useful.

    Thanks for any assistance.

    Best regards,

    Tom Dawson
  2. SgtWookie


    Jul 17, 2007
    It's going to be tough to see what you're talking about without having the schematic and error messages handy.