Hey all,

I am working on a fairly high-end power supply design with purposely-exaggerated specifications...just to see what can be done. 1mV resolution on voltage output from 0 - 30V, 1 mA current limit resolution with maximum of 3 amps out, yadda yadda.

Basically, it's a bench top power supply. I wanted it to be digitally-variable and a DAC was going to be employed for this purpose.

I'll use a rock-solid reference and careful layout, low TC/tolerance resistors, low offset opamps, you know...all that.

My issue is with the DAC. On every single datasheet I've seen for DACs that aren't $50 apiece, they claim to have a "zero code error" or "zero code offset" of 1 mV, or 3 mV, or a few LSBs (I'm looking at 16-bit DACs).

My question is: If I want a true zero-output (as in, 100uV if the resolution of my output is to be 1 mV), do these parts exist? Or, what tricks or circuit techniques are used to ensure a nice, linear output for all bit-codes from zero to full-scale?

Alternatively, does anyone have any advice on what other ways there are to implement DAC functionality? Kelvin-Varley dividers are a bit too complex/high end for this, but I have contemplated using PWM...etc.

Thanks much in advance!

Paul

 

I think typically you add a pot to adjust the zero point at the op amp input that's at the DAC output. If you scale the pot so it has, say a 20mV adjustment range (or enough to cover the max. offset error of the DAC), then you can adjust to power supply output to 0V when the DAC is set to zero. Of course you want this pot to get its voltage from your accurate reference.

 

Thank you for the response. That seemed to be what needed done, but one of the goals of the supply was to alleviate any need for trimming...apparently you just can't get away from it sometimes!

As per the trim pot, if I adjust this pot such that the zero-code error produces 0.000 VDC at the buffer amp's output, will this shift all bits upwards/downwards by that offset?

In other words, the name of this offset on the DAC datasheet is "zero-code" offset - does this mean that it exists only at code zero, or will it exist at 0x0000 as well as 0x0005 as well as 0x3543 etc...the reason I ask is that I also see specs such as "gain error", "differential nonlinearity", and "integral nonlinearity"...and I assume that, if I've already over-estimated my resolution by a factor of ten, those other errors, such as 1 or 2 LSBs for each, will still not be enough to destroy my 1 mV resolution I seek...but I wanted to make sure the zero-code offset adjust wouldn't swamp it all.

Thanks very much again

 

As you noticed, the cost of the more accurate DACs, which may not require offset correction, is high.

You want to adjust the offset at the power supply output. Is that the buffer output?

I believe the zero-code offset is for all bits, so if you null that out, all the other bit outputs will be correct within their gain and non-linearity errors.

 

Crutschow-

Thanks for the bit on the zero-code. I can live with that

Basically, the user keys in his or her desired voltage level and current-limit, and then hits "set". The PIC or whatever MCU in use will then store the values and update the DACs. At this point, the Vref will be decimated into, say, 32,768 counts off of a +5v reference for +2.500 +/- 100uV or so. This signal is then meticulously guided to the output buffer amplifier, which will be the usual bipolar output with voltage and current monitoring. The plan is for the entire power supply, both output voltage and current-limiting, to be slaved to the reference, which will be designed to be very stable and out of the way of thermal gradients. "bipolar output" as in bipolar transistor, not dual polarity...

So, in closing (unless you want me to elaborate on something else?), Vref sits happily in its ovened enclosure and is scaled carefully with a temperature-stable (offset-wise) opamp and low-TC gain resistor array. I'll adjust that manually for either +5v or +7v output (or whichever it ends up being, not sure yet.) This reference voltage will be fed into an opamp whose one input is connected to a slim trim circuit (+/-3 - 5 mV full scale on the pot) and from there into the buffer amplifier stage. All along, each stage confirms the proper voltage getting to the proper input by means of sense feedback to alleviate PCB trace resistance and other things. That extra opamp just kills me. That entire chip has to exist because of a lousy 1mV. Gahhh just kills me. I suppose an alternative is to use a bipolar DAC and digitally-read the output and apply nulling via a digital offset, but that's even more of a cluster...

 

It's easy enough to set it to 1mV resolution, but good luck getting it to deliver the voltage with 1mV precision at the load.

 

All you need do is to add a small bias (derived from your zero drift ref) to your op amp chain. Then zero in to your DAC will NOT be zero out, you need to go to some higher number to get to zero (so zero+1 makes the first voltage output step).

That offset number gets stored in the EEPROM of the PIC as a calibration constant.

No pots to turn, just some code to set & store & use the number.

 

You need to know about integral and differential non-linearity so that you are well aware of the limitations of DACs.

Integral non-linearity is the deviation of the input vs output function from a straight line. In a perfect DAC one would expect the output voltage of a 16-bit DAC to be equal to N x Vref/65536 where N is the digital input. In real world DAC this is not the case and there is an error at some or every value of N.

Differential non-linearity refers to the deviation of each voltage step from the expected value of Vref/65536 for a 16-bit DAC. In an ideal 16-bit DAC, each voltage step would be of equal size, equal to Vref/65536. In a real DAC there is variation from step to step across the entire range of the DAC.

If you are looking for better results, consider using a timed constant current source. Such a DAC uses a constant current source to charge a capacitor for a given length of time using a timer clocked by a crystal controlled oscillator. Since the output voltage is equal to the current I x time/C, integral and differential non-linearity is much reduced compared to a classic resistor ladder DAC.

 

RB, I have precision voltage and current measurement techniques for that I'm sure it will be quite a task anyway, though! I will learn a lot from this project.

Ernie, this is a good thought. I contemplated this (and I think I hinted at it in the original post). Although, part of the goal of this project was to simply assemble, program and have voltage and current at the specified accuracy and precision, so with the software method, unless an ADC is used, I would have to store separate constants for each power supply (I do plan on selling them...at least I hope to). I'm not sure how this zero-code error drifts over time either. I'm looking for a solution that will inherently work every time without adjustment...at least, I aim for that. If I have to trim with an analog pot once, I'm O.K. with that...as long as everything else falls into place accordingly.

MrChips, after the original post late last night, I did indeed consult a TI application note and I read about zero-code offset error, DNL, INL and gain error as being the four parameters that govern the awesomeness (absolute accuracy) of a particular DAC. I think I have a scheme in mind that will alleviate a majority of the issues using lower-res DACs.

 

It appears as though I edited the original post and deleted the software-tune portion, but between my brain and this post, I did contemplate it in a document that I'm writing up for the project.

Thank you all for the input, very helpful.

 

.......................
This signal is then meticulously guided to the output buffer amplifier, which will be the usual bipolar output with voltage and current monitoring. The plan is for the entire power supply, both output voltage and current-limiting, to be slaved to the reference, which will be designed to be very stable and out of the way of thermal gradients.

..............................This reference voltage will be fed into an opamp whose one input is connected to a slim trim circuit (+/-3 - 5 mV full scale on the pot) and from there into the buffer amplifier stage. All along, each stage confirms the proper voltage getting to the proper input by means of sense feedback to alleviate PCB trace resistance and other things. That extra opamp just kills me. That entire chip has to exist because of a lousy 1mV. Gahhh just kills me. .......................

I don't understand the need for a extra op amp. Or don't you have any op amps in the design? If so, how do you plan
on doing the "sense feedback" or have the output voltage "slaved to the reference"?