- Joined Sep 26, 2013
"op amp 6"???In the following each of the inverters are shown with ins and outs but no connection with Vdd or Vss
In a functioning circuit like this
They are shown as being connected op amp 6.
I do not get it.
I am also at a loss how to set this up in LtSpice
The CD4000 and 74HCxx digital models I have for LTspice do not show power and ground connections on the schematic.I am also at a loss how to set this up in LtSpice
ALL of the physical inverters on the chip have power and ground connections. Just as all logic gates and opamps and comparators and other electronic components do. Logic devices have to be powered in order to work properly.So on the 4069 circuit the connections to Pin 7 and Pin 14 on N6 is just the convention for indicating a common power source to all the inverters in the circuit. (not actually connected to N6 as the inverter only has an IN and an OUT.
Power and ground (return) are understood, and if the simulation software does not understand that then it is of marginal value. I have designed a lot of digital circuits that worked the first time that they were wired like the drawing. Why waste time with a simulator???ALL of the physical inverters on the chip have power and ground connections. Just as all logic gates and opamps and comparators and other electronic components do. Logic devices have to be powered in order to work properly.
But drawing all of those power and ground connections significantly clutters the diagram. Plus, if each gate has a power and ground node, what happens if someone attempts to power four of the inverters from one supply and the remaining two from another?
There are many approaches to dealing with this. Some put explicit power/ground connections on just one of the gates and use the library tools to share them with other gates. Some make the power and ground connections hard tied to specific global net names. There are several other approaches as well. They are each a compromise between simplicity and flexibility for the users of the library.
A timing chart showing output changes based on input changes is a fairly simple way of validating logic. It does consume a bit of paper, but it is quite powerful.It has the advantage of often making errors visible earlier and with less effort, and it can be verified as correctly representing a circuit, while taking less time than entering a model in a simulator. Even better, it is a useful tool for verifying logic as a circuit is created.Well obviously not all of us are as good at designing mistake free designs as you.
Really? Let's see, I've designed circuits for systems that had 2.5 V, 3.3 V, and 5.0 V logic all in the same circuit. A simulator that only offered a single, fixed logic power wouldn't have been marginal, it would have been useless. Most of the circuits I've designed had a different return node than most of the rest of the circuit and further needed the substrate bulk connected tied to a separate net from the return power rail. A simulator that assumed that these were tied together would have been useless.Power and ground (return) are understood, and if the simulation software does not understand that then it is of marginal value.
And were you willing to guarantee, to a customer about to pay the better part of a million dollars to have chips fabricated with your design, that it would work the first time over all supply voltages and temperatures, even down to liquid nitrogen, and across all four of the foundry's process corners and, if they didn't, that you would do the redesign and submission for free? We were -- that was our standard guarantee.I have designed a lot of digital circuits that worked the first time that they were wired like the drawing. Why waste time with a simulator???
The number of players in the ASIC world has definitely dwindled. As the design rules have gone down, the cost of the fab have gone through the roof. Multi-billions of dollars for a fab that has to recoup most of that investment in just a few years time.It might be different today.....but 20 yrs.ago I could order our own designed IC chips. If I recall, the min order was 500 units. It was a wired headset transceiver with vox....for aircraft helmets.
This was analog.....we would solder a breadboard working prototype circuit to spec. Send this circuit with details to a job contracted IC designer. After IC design approval, the IC guy would get bids from several chip manufacturers. So we had a design cost and manufacture cost.
But the beauty was we had control of price. It was custom work. So we might use 300 units out of 500.....but the chip "NUT" would be in 300 unit cost.
If I recall correctly, there were many custom chip manFs. Maybe not now.
Posters here often get into side quibbles about the thread subject and sometimes sort of go off-rail, but don't let that affect your posts.My God this has really gone awry ........
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