# IC Schematics - Convention and Reality

#### teliocide

Joined Sep 26, 2013
55
In the following each of the inverters are shown with ins and outs but no connection with Vdd or Vss

In a functioning circuit like this

They are shown as being connected op amp 6.

I do not get it.
I am also at a loss how to set this up in LtSpice

Thanks

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#### WBahn

Joined Mar 31, 2012
24,854
In the following each of the inverters are shown with ins and outs but no connection with Vdd or Vss

In a functioning circuit like this

They are shown as being connected op amp 6.

I do not get it.
I am also at a loss how to set this up in LtSpice

Thanks
"op amp 6"???

I see six inverters. Inverters are NOT op amps.

The power connections to the six inverters on the die are via pins 7 (Vss) and 14 (Vdd). Since all of the inverters on on a single die, there no need for separate power/ground connections to each one.

In your second drawing, the power ground connections are shown on just one of the six inverters -- the rest are inferred via the netlist.

How you set it up in a particular simulator depends both on the simulator and on the parts library involved.

#### teliocide

Joined Sep 26, 2013
55
So on the 4069 circuit the connections to Pin 7 and Pin 14 on N6 is just the convention for indicating a common power source to all the inverters in the circuit. (not actually connected to N6 as the inverter only has an IN and an OUT.

#### crutschow

Joined Mar 14, 2008
23,544
I am also at a loss how to set this up in LtSpice
The CD4000 and 74HCxx digital models I have for LTspice do not show power and ground connections on the schematic.
They are hidden connections.
They require a power supply connected to ground on the schematic with a Vdd node name on the supply plus node.

Here's an example of a CD4017 circuit in LTspice:

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#### WBahn

Joined Mar 31, 2012
24,854
So on the 4069 circuit the connections to Pin 7 and Pin 14 on N6 is just the convention for indicating a common power source to all the inverters in the circuit. (not actually connected to N6 as the inverter only has an IN and an OUT.
ALL of the physical inverters on the chip have power and ground connections. Just as all logic gates and opamps and comparators and other electronic components do. Logic devices have to be powered in order to work properly.

But drawing all of those power and ground connections significantly clutters the diagram. Plus, if each gate has a power and ground node, what happens if someone attempts to power four of the inverters from one supply and the remaining two from another?

There are many approaches to dealing with this. Some put explicit power/ground connections on just one of the gates and use the library tools to share them with other gates. Some make the power and ground connections hard tied to specific global net names. There are several other approaches as well. They are each a compromise between simplicity and flexibility for the users of the library.

#### MisterBill2

Joined Jan 23, 2018
4,066
ALL of the physical inverters on the chip have power and ground connections. Just as all logic gates and opamps and comparators and other electronic components do. Logic devices have to be powered in order to work properly.

But drawing all of those power and ground connections significantly clutters the diagram. Plus, if each gate has a power and ground node, what happens if someone attempts to power four of the inverters from one supply and the remaining two from another?

There are many approaches to dealing with this. Some put explicit power/ground connections on just one of the gates and use the library tools to share them with other gates. Some make the power and ground connections hard tied to specific global net names. There are several other approaches as well. They are each a compromise between simplicity and flexibility for the users of the library.
Power and ground (return) are understood, and if the simulation software does not understand that then it is of marginal value. I have designed a lot of digital circuits that worked the first time that they were wired like the drawing. Why waste time with a simulator???

#### crutschow

Joined Mar 14, 2008
23,544
Why waste time with a simulator?
Well obviously not all of us are as good at designing mistake free designs as you.

#### MisterBill2

Joined Jan 23, 2018
4,066
Well obviously not all of us are as good at designing mistake free designs as you.
A timing chart showing output changes based on input changes is a fairly simple way of validating logic. It does consume a bit of paper, but it is quite powerful.It has the advantage of often making errors visible earlier and with less effort, and it can be verified as correctly representing a circuit, while taking less time than entering a model in a simulator. Even better, it is a useful tool for verifying logic as a circuit is created.

#### WBahn

Joined Mar 31, 2012
24,854
Power and ground (return) are understood, and if the simulation software does not understand that then it is of marginal value.
Really? Let's see, I've designed circuits for systems that had 2.5 V, 3.3 V, and 5.0 V logic all in the same circuit. A simulator that only offered a single, fixed logic power wouldn't have been marginal, it would have been useless. Most of the circuits I've designed had a different return node than most of the rest of the circuit and further needed the substrate bulk connected tied to a separate net from the return power rail. A simulator that assumed that these were tied together would have been useless.

We actually had three levels of symbols for our standard logic cells. The lowest had everything pinned out, including the substrate bulk connection. The next level had these tied to parameterized signals so that we could define which power/ground/bulk nets they went to in the netlist without having to clutter up the schematics with the pins (but rather by setting attributes on the symbols), and the top level had power tied to the global VddD, ground tied to VssD, and the bulk tied to Vss. The latter were used when we only had a single digital supply rail.

I have designed a lot of digital circuits that worked the first time that they were wired like the drawing. Why waste time with a simulator???
And were you willing to guarantee, to a customer about to pay the better part of a million dollars to have chips fabricated with your design, that it would work the first time over all supply voltages and temperatures, even down to liquid nitrogen, and across all four of the foundry's process corners and, if they didn't, that you would do the redesign and submission for free? We were -- that was our standard guarantee.

#### MisterBill2

Joined Jan 23, 2018
4,066
WBahn, Oh Wow No, I don't design chips, and I am glad of that. For our company an order of 10 machines was a huge order, and each machine might have 2 or three custom, or standard, circuit boards. I was always careful to design with logic and analog chips that were available from multiple sources so that nothing was ever dependent on a single sourced part. Just totally different from your line of business, because those complex chips have so much NRE that production runs have to be really big. So we work in two different worlds, it seems. And that is fine, because who would need a thousand specialized machines to check products coming off the end of a production line one a minute?
We never would consider custom ICs, because they would never be cost effective. One person did point out that he could get all of the functionality into one IC and save us almost $5 per unit, for a cost of about$25,000. That was far greater than our entire IC budget for the year. And that included a large production run of 35 laser speed measuring systems, whose IC count was 5 for the sensor and three for the display.
So for us and for our operation a timing chart was the way to go. IC design, especially the big ones, is an entirely different world, not just a different ball game. Of course our products did all come with a similar guarantee.

#### DickCappels

Joined Aug 21, 2008
5,952
This might useful to you, it is an expansion of crutschow's explanation in post #4.

Right-mouse-click on the device in your schematic. A dialog will be shown.
Enter the parameter(s) into any field from "Value" to "SpiceLine2".

Vhigh=5 Vlow=0 Ref=1.5
Trise=5n Tfall=5n Td=5n

"Ref" is the threshold. Default is (Vhigh+Vlow)/2

The above is from Google Groups

#### BR-549

Joined Sep 22, 2013
4,938
It might be different today.....but 20 yrs.ago I could order our own designed IC chips. If I recall, the min order was 500 units. It was a wired headset transceiver with vox....for aircraft helmets.
This was analog.....we would solder a breadboard working prototype circuit to spec. Send this circuit with details to a job contracted IC designer. After IC design approval, the IC guy would get bids from several chip manufacturers. So we had a design cost and manufacture cost.

But the beauty was we had control of price. It was custom work. So we might use 300 units out of 500.....but the chip "NUT" would be in 300 unit cost.

If I recall correctly, there were many custom chip manFs. Maybe not now.

#### WBahn

Joined Mar 31, 2012
24,854
It might be different today.....but 20 yrs.ago I could order our own designed IC chips. If I recall, the min order was 500 units. It was a wired headset transceiver with vox....for aircraft helmets.
This was analog.....we would solder a breadboard working prototype circuit to spec. Send this circuit with details to a job contracted IC designer. After IC design approval, the IC guy would get bids from several chip manufacturers. So we had a design cost and manufacture cost.

But the beauty was we had control of price. It was custom work. So we might use 300 units out of 500.....but the chip "NUT" would be in 300 unit cost.

If I recall correctly, there were many custom chip manFs. Maybe not now.
The number of players in the ASIC world has definitely dwindled. As the design rules have gone down, the cost of the fab have gone through the roof. Multi-billions of dollars for a fab that has to recoup most of that investment in just a few years time.

There are a handful of places that will do multi-project wafer (MPW) runs where your design is placed on a reticle with many others. You normally get five to ten die from one of those. I've been out of that world for about a decade now (still do some design work for my old employer from time to time, but don't get involved with the fab interface at all any more) and at that time about the cheapest you could even do that was about $20k. When I first started there in 1995, you could actually do it for as low as$800.

Now, even if you have a design for which 2 um (or larger) rules would be adequate, it's pretty much impossible to find a fab that is still using those rules and even harder to find one that will do MPW runs.

#### teliocide

Joined Sep 26, 2013
55
My God this has really gone awry ........

I ask questions because I lack knowledge and experience but have interest.
I have numerous qualifications but none that relate to electronics.

Electronics is ubiquitous and inescapable.

It is a shame that life is so short so I can never become an expert in everything.
There would be no need to annoy people with my ignorant questions.

So you (plural) can puff up your feathers and demonstrate your intellectual supremacy. .

A true expert no matter how gifted has had to do some of the hard yards.
Satisfaction awaits you - just allow a few crumbs of your wisdom to drop from the table.
Then us Plebs have something tangible to fight over.

#### BR-549

Joined Sep 22, 2013
4,938
Did you understand posts 1 thru 5? On a schematic.....on IC, OP-AMP, and other circuits........the power pins and power supply bypassing are not shown at symbol location. This is for clarity. When looking at a schematic....we are tracing the signal.....not the power supply. The power supply is considered house keeping. We don't analyze IC circuits like we would a transistor circuit.

You will find representative power rails and bypassing caps.....usually in the power supply section of schematic.

Does that make any sense to you?

#### crutschow

Joined Mar 14, 2008
23,544
My God this has really gone awry ........
Posters here often get into side quibbles about the thread subject and sometimes sort of go off-rail, but don't let that affect your posts.
Just ignore the irrelevant.

#### Bordodynov

Joined May 20, 2015
2,430
See

#### MisterBill2

Joined Jan 23, 2018
4,066
The beauty of this site is that civil discourse is not stomped on nor forbidden. Certainly it went a bit off the original question, and certainly my remark about simulation was challenged, but in a decent manner, pointing out that what does not fit in some worlds is vital in others..
BUT, returning to the original question, I think, the device model that would include the power connections would be quite large, and totally distract from the common use of simulations. Most digital designs include enough bypassing and voltage stablizing effort that power connections are not included in the logic simulation. Of course, that does not include any design work within a specific integrated circuit, which, again, is a totally different world.

#### teliocide

Joined Sep 26, 2013
55
Thanks to all
Primarily I am here to learn.

I have a story.

20 years ago I went to the Hanoi university to learn Vietnamese.
For white devils, like myself, this is very very difficult.

After a lot of hard study I realized that the only Vietnamese people that could understand what I spoke were Vietnamese people that spoke English. Extremely useful NOT!

I see an analogy with this forum.

When a novice asks a questions the experts here have no real idea of the position of ignorance the novice is speaking from.
The answers provided tend to be "club speak" ie expert to expert. The poor old novice is drowned in unfamiliarity and alien terms.

I understand that the quality of the answer is determined by the clarity of the question.

But when you don't speak the language how can one ask precise questions.

#### eetech00

Joined Jun 8, 2013
1,726
Hi

There are many ways to do this in LTspice. Here's another way.
This approach requires a special library "CD4000_v.lib" from the LTspice Yahoo group. This library supports symbols with or without supply pins.
It also requires special symbols, one with supply pins, and one without supply pins.

See image below.

eT