hey guys...

I have a question here with regards to IC design..

Why is it that EDAs do NOT automate the Layout stage of a design? So lets say you're working with a circuit on ORCAD or something.. and you have all the components and the nets wired and you obtain a netlist.. why do we have to go through the layout process?

Another question.. does anyone know of a reference (webiste preferably) or e-book which talks about the concepts of IC Layout ? I have never done layout before and am really interested in learning the main concepts and design rules of thumb...

Thanks guys

 

Try this link to the tutorial by Jones.

John

 

If you mean layout of components on a circuit board and not layout of the silicon in a IC, then I think there exist some programs capable of laying the parts. But these can be used only for few parts, because with more the automated results are often simply wierd and it is better to use human inteligence.

 

Thanks for the replies guys..

I guess I wasn't very clear.. I meant Integrated Circuit layouts on SILICON...

 

Autorouters are seldom used because the simulated anealing algorithms are not guaranteed to terminate with acceptable results. It is unknown weather these algoithms can terminate in polynomial time. It gets much worse as the feature size gets smaller and you try to pack more functions into the same silicon area.

The best results are achieved with regular structures like RAM, and ROM for microcode. Random logic and arbitrary state machines really put a strain on autorouters. Just my experience; your mileage may vary.