# How to reduce the transient response of integrator output

Discussion in 'Homework Help' started by shengwuei, Jun 4, 2014.

1. ### shengwuei Thread Starter Member

Aug 22, 2008
17
0
Hi,

I am designing an integrator which integrate part of a sine wave periodically, and then the integrated voltage is held on a capacitor through an analog switch. The schematic of integrator as below :

U1/R1/C1 forms the integrator, while the analog switch S3 sets the output of integrator to zero when closed. U3 is a buffer. The "set_to_zero" signal goes high periodically at 40kHz frequency, 10% duty cycle. So the integrator integrates its input waveform / set to zero output periodically at 40kHz. Simulated results as below:

red : set_to_zero
orange : input waveform, 10kHz/100mVpp sine wave
greed : integrator output
blue : hold the integrator output on a capacitor

My problem is, there is a transient peak on integrator output every time integrator is toggled from zero output to integrated output, the peak lasts about 2us

The peak somehow effects the integrated voltage of this circuit, the only thing I know for now is increasing the supply voltage of integrator(U1) could reduce the peak, but it is not good enough, I would like to ask for suggestions about this problem, thanks in advance.

2. ### DickCappels Moderator

Aug 21, 2008
3,836
1,043
A couple of ideas:
Maybe its that you don't have a resistor to limit the current into the summing node. It might also be that the risetime of your pulse is way too fast, so try rolling that off with a single RC filter.

Last edited: Jun 4, 2014
3. ### Experimentonomen Member

Feb 16, 2011
331
46
Or that the integrators capacitor is only 0.5pF, i'd say you need atleast a couple of nF, prolly up to a few hundred nF.

4. ### ronv AAC Fanatic!

Nov 12, 2008
3,657
2,800
Is there something missing from your schematic?

I see the blue trace that says "hold" but no circuit to hold the sample, so I'm thinking something is missing. What is C9 doing?

But all those questions aside: it is a wide bandwidth op amp and should probably have lower resistor values in the feedback path so stray capacitance doesn't bother it quite so much. Try 10X smaller R's and 10X larger C and see if that helps.

5. ### Experimentonomen Member

Feb 16, 2011
331
46
0.5pF is literally the same as having no capacitor at all = what you have is not an integrator at all, but rather a 2x gain inverting amplifier.

And i'd say you also need a pullup resistor on pin 8 as thats a active low "power down" input pin.

It also seems multisim doesent understand the circuit as you should get a amplified version of your sine wave on the output if you disconnect the reset "switch"

6. ### AnalogKid AAC Fanatic!

Aug 1, 2013
5,589
1,586
What is the function of C9? It is almost connected to the U1 output, where it can cause transient distortion. Discharging this cap into the U1 inverting node would cause a spike in the output that changes with the slope of the sampled waveform, exactly like the blue trace.

Also, the input is a sinewave, and the output is a stepped sinewave (with delay). Since you have a known periodic input, how is what you are doing different from a straight-up sample and hold?

ak

7. ### crutschow Expert

Mar 14, 2008
16,230
4,341
Some of those waveforms don't seem to agree with your schematic. Can you point out where in the circuit those waveforms appear.

8. ### ronv AAC Fanatic!

Nov 12, 2008
3,657
2,800
I think you are making a sample and hold. I think you might do better switching the output rather than the input of the high speed op amp.
Maybe something like this?

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