How to mix BPSK signal with high frequency carrier

Thread Starter

Nguyễn Hà 2

Joined Feb 26, 2019
8
Hi everyone,.
I'm trying to create a basic signal modulator. I used FPGA to generate bpsk modulation signal with a width of about 15MHz.
Now how do I mix this signal with a carrier? Can I use circuit or mixer to do that?
for example, the carrier has a frequency of 942.5MHz
Thanks for your help !
 

cariban

Joined Aug 14, 2018
69
Hi everyone,.
I'm trying to create a basic signal modulator. I used FPGA to generate bpsk modulation signal with a width of about 15MHz.
Now how do I mix this signal with a carrier? Can I use circuit or mixer to do that?
for example, the carrier has a frequency of 942.5MHz
Thanks for your help !
You have two more steps to go. Refer to the attached diagram. FPGA feeds digital baseband signal to DAC. The interface between FPGA and DAC is not shown.
1. You need a digital pulseshaping filter for the BPSK signal to suppress the side-lobes. Most common used pulse is square-root raised cosine pulse.

2. You need a DAC to convert the digital signal generated by FPGA to analog signal, then mix it with the carrier either by a mixer or a modulation IC.
 

Attachments

Last edited:

Thread Starter

Nguyễn Hà 2

Joined Feb 26, 2019
8
You have two more steps to go. Refer to the attached diagram. FPGA feeds digital baseband signal to DAC. The interface between FPGA and DAC is not shown.
1. You need a digital pulseshaping filter for the BPSK signal to suppress the side-lobes. Most common used pulse is square-root raised cosine pulse.

2. You need a DAC to convert the digital signal generated by FPGA to analog signal, then mix it with the carrier either by a mixer or a modulation IC.
Thank you very much ! What you say is very useful to me.
I learn on www.ni.com and used to this below model.


IF frequency is generated by the txdac AD9767. Type of bpsk signal generated from matlab and put into txdac by FPGA. This signal is passed through the square-root raised cosine filter in matlab.
I create LO frequency with ADF4350 module.

upload_2019-2-28_8-44-1.png

My problem is not knowing how to use the mix is right. There are many problems with synchronization and phase-locked loop here that I don't know. I found it not as simple as simulating the signal in matlab. I have not found a solution to this problem.
I'm looking forward to ur help and thank you very much ^^.
 

Attachments

cariban

Joined Aug 14, 2018
69
Thank you very much ! What you say is very useful to me.
I learn on www.ni.com and used to this below model.


IF frequency is generated by the txdac AD9767. Type of bpsk signal generated from matlab and put into txdac by FPGA. This signal is passed through the square-root raised cosine filter in matlab.
I create LO frequency with ADF4350 module.

View attachment 171156

My problem is not knowing how to use the mix is right. There are many problems with synchronization and phase-locked loop here that I don't know. I found it not as simple as simulating the signal in matlab. I have not found a solution to this problem.
I'm looking forward to ur help and thank you very much ^^.
AD9767 has two channels and is designed for I/Q modulation. So the mixer/modulation chip should have both I and Q channel as well. Even though BPSK needs only I channel, it is better to consider more generic platform for other modulation like QAM, APSK, OFDM...The digital baseband signal needs to be 2-4 times over-sampled in order to filter out alias in an easier way. This you may have known.

You don't need the digital I/Q mixer inside FPGA since you only need to feed the DAC with the baseband signal (composed by I and Q).

About the modulation chip, there are many choices from Texas, Analog, Maxim... Some chips even have embedded PLL. It is also not difficult to design discrete PLL circuit. Analog has a very good fee tool called ADIsimPLL for PLL design.
 

Thread Starter

Nguyễn Hà 2

Joined Feb 26, 2019
8
AD9767 has two channels and is designed for I/Q modulation. So the mixer/modulation chip should have both I and Q channel as well. Even though BPSK needs only I channel, it is better to consider more generic platform for other modulation like QAM, APSK, OFDM...The digital baseband signal needs to be 2-4 times over-sampled in order to filter out alias in an easier way. This you may have known.

You don't need the digital I/Q mixer inside FPGA since you only need to feed the DAC with the baseband signal (composed by I and Q).

About the modulation chip, there are many choices from Texas, Analog, Maxim... Some chips even have embedded PLL. It is also not difficult to design discrete PLL circuit. Analog has a very good fee tool called ADIsimPLL for PLL design.
I will learn more. I have AD8342 mixer module. I tried mixing the IF signal from AD9767 with the carrier signal from ADF4350 but the output signal spectrum is not correct compared to the bpsk spectrum I know.

upload_2019-3-1_11-26-19.png

The signal has been passed through band pass filter from 925-960MHz.
The peak amplitude of the carrier is always high and I have no way to eliminate it.
Due to hardware limitations, I can only do so.
Tell me why so?
Thank you very much ^^!
 
Last edited:

cariban

Joined Aug 14, 2018
69
LO_RF_leakage.PNG
I will learn more. I have AD8342 mixer module. I tried mixing the IF signal from AD9767 with the carrier signal from ADF4350 but the output signal spectrum is not correct compared to the bpsk spectrum I know.

View attachment 171210

The signal has been passed through band pass filter from 925-960MHz.
The peak amplitude of the carrier is always high and I have no way to eliminate it.
Due to hardware limitations, I can only do so.
Tell me why so?
Thank you very much ^^!
This is quite normal for I/Q modulator, or for any mixer. There always exists leakage from LO port to RF port. Fortunately there is a way to reduce the leakage. The idea it to add a signal in the RF path. The signal has the same frequency and same amplitude with the LO leakage, but the phase is 180 degrees shifted. To have the exact frequency, you must feed the LO to FPGA. Also you need a calibration procedure, i.e. tuning the amplitude and phase of the added sinusoidal LO signal to minimize the total LO leakage. Note that the LO leakage varies from chip to chip and varies from temperature to temperature, you need to do calibration for each chip and at many different temperature points.

To be able to do LO leakage cancellation, you must have an I/Q modulator. AD8342 is not an I/Q modulator. You may consider to change it.
 

cariban

Joined Aug 14, 2018
69
I will learn more. I have AD8342 mixer module. I tried mixing the IF signal from AD9767 with the carrier signal from ADF4350 but the output signal spectrum is not correct compared to the bpsk spectrum I know.

View attachment 171210

The signal has been passed through band pass filter from 925-960MHz.
The peak amplitude of the carrier is always high and I have no way to eliminate it.
Due to hardware limitations, I can only do so.
Tell me why so?
Thank you very much ^^!
Btw, have you used SR-RC pulse shaping for the BPSK signal? If yes, the spectrum should look like this. There may be a spike (LO leakage) in the middle of the band.

spectrum.png
 

Thread Starter

Nguyễn Hà 2

Joined Feb 26, 2019
8
Btw, have you used SR-RC pulse shaping for the BPSK signal? If yes, the spectrum should look like this. There may be a spike (LO leakage) in the middle of the band.

View attachment 171222
I follow these steps:
- In matlab
+ Create array of data bits
+ Transform nrz (1 to 1; 0 to -1) creates x_bit string
+ Root raised cosine filter root raised cosine filter: rolloff = 0.3; span = 8; sps = 4; b = rcosdesign(rolloff, span, sps); x = upfirdn(x_bit, b, sps);
+ Then I sampled and put into the AD9767. I took an AD9767 analog output into the mixer
- the LO signal I created from ADF4350 however I only took the signal from RF_OUT_A + into the mixer
The FPGA has a clock input from a 50Mhz quartz and generates 25Mhz to put into ADF4350 for frequency synchronization. Is this true?
I have to learn more and probably have to follow this model. You can point out my mistakes :)) Thank you for your help !
upload_2019-3-1_17-29-31.png
 

cariban

Joined Aug 14, 2018
69
I follow these steps:
- In matlab
+ Create array of data bits
+ Transform nrz (1 to 1; 0 to -1) creates x_bit string
+ Root raised cosine filter root raised cosine filter: rolloff = 0.3; span = 8; sps = 4; b = rcosdesign(rolloff, span, sps); x = upfirdn(x_bit, b, sps);
+ Then I sampled and put into the AD9767. I took an AD9767 analog output into the mixer
- the LO signal I created from ADF4350 however I only took the signal from RF_OUT_A + into the mixer
The FPGA has a clock input from a 50Mhz quartz and generates 25Mhz to put into ADF4350 for frequency synchronization. Is this true?
I have to learn more and probably have to follow this model. You can point out my mistakes :)) Thank you for your help !
View attachment 171226
The diagram looks correct for me. I would suggest:
1. Double check the spectrum of the digital signal after pulse shaping. It is sufficient to just use Matlab;

2. Use spectrum analyzer to double check the baseband analog signal from DAC, after the lowpass anti-alias filter.

Note that the LO clock does NOT need to be generated by FPGA. FPGA will produce extra jitter on the clock. In your case you may use the 50MHz clock as the reference clock for PLL. Since the FPGA and PLL are referred to the same clock source, LO leakage cancellation is possible.
 

Thread Starter

Nguyễn Hà 2

Joined Feb 26, 2019
8
The diagram looks correct for me. I would suggest:
1. Double check the spectrum of the digital signal after pulse shaping. It is sufficient to just use Matlab;

2. Use spectrum analyzer to double check the baseband analog signal from DAC, after the lowpass anti-alias filter.

Note that the LO clock does NOT need to be generated by FPGA. FPGA will produce extra jitter on the clock. In your case you may use the 50MHz clock as the reference clock for PLL. Since the FPGA and PLL are referred to the same clock source, LO leakage cancellation is possible.
This is the same signal after I give the RRC filter and its base band spectrum.
upload_2019-3-2_15-36-23.png
upload_2019-3-2_15-37-14.png

I think my problem is in the mixer and LO generator because I didn't do it right.
 

cariban

Joined Aug 14, 2018
69
It seems that the sidelobes are too high. What is the pulse length of the shaping filter? Maybe you used too short pulse length.

To verify the mixer, it is better to start with single carrier. You may just simply send DAC a sinusoidal wave, for example 10MHz. Then check the spectrum of the I/Q modulator output. The correct spectrum should be only LO+10MHz present, plus some very low level spurs.
 

Thread Starter

Nguyễn Hà 2

Joined Feb 26, 2019
8
It seems that the sidelobes are too high. What is the pulse length of the shaping filter? Maybe you used too short pulse length.

To verify the mixer, it is better to start with single carrier. You may just simply send DAC a sinusoidal wave, for example 10MHz. Then check the spectrum of the I/Q modulator output. The correct spectrum should be only LO+10MHz present, plus some very low level spurs.
You can tell me what this filter parameter optimization when? I have changed the parameters and have the following results
rolloff = 0.1; span = 16; sps = 4; b = rcosdesign(rolloff, span, sps);
upload_2019-3-4_8-42-30.png

rolloff = 0.1; span = 32; sps = 4; b = rcosdesign(rolloff, span, sps);
upload_2019-3-4_8-44-33.png
When I leave the rolloff value high, sidelobes are also high.

I will experiment with ADL5375 mixer.
 

Thread Starter

Nguyễn Hà 2

Joined Feb 26, 2019
8
I did not pay attention to my carrier signal creating noise like this and I don't know how to destroy it:
upload_2019-3-4_9-7-46.png

This may be the reason that the signal spectrum has a maker like figure # 5. This is just one cause in many of my errors: v
 
Last edited:

cariban

Joined Aug 14, 2018
69
You can tell me what this filter parameter optimization when? I have changed the parameters and have the following results
rolloff = 0.1; span = 16; sps = 4; b = rcosdesign(rolloff, span, sps);
View attachment 171511

rolloff = 0.1; span = 32; sps = 4; b = rcosdesign(rolloff, span, sps);
View attachment 171512
When I leave the rolloff value high, sidelobes are also high.

I will experiment with ADL5375 mixer.
Use Matlab to plot the spectrum. Then optimize the pulse length (the span parameter) and over-sampling rate (the sps parameter) until satisfied. I feel there is something wrong with the output spectrum from DAC, for roll-off factor of 0.1, the edge should be much steeper. Also the inband spectrum should be quite flat.
 

cariban

Joined Aug 14, 2018
69
I did not pay attention to my carrier signal creating noise like this and I don't know how to destroy it:
View attachment 171513

This may be the reason that the signal spectrum has a maker like figure # 5. This is just one cause in many of my errors: v
Is this spectrum of the single-carrier mode? Try to move the baseband carrier and watch if the spurs follow the carrier. It seems that the spurs are from LO clock. Just measure the spectrum of LO feeding to I/Q modulator.
 

Thread Starter

Nguyễn Hà 2

Joined Feb 26, 2019
8
Use Matlab to plot the spectrum. Then optimize the pulse length (the span parameter) and over-sampling rate (the sps parameter) until satisfied. I feel there is something wrong with the output spectrum from DAC, for roll-off factor of 0.1, the edge should be much steeper. Also the inband spectrum should be quite flat.
upload_2019-3-6_8-49-57.png
upload_2019-3-6_8-51-35.png
upload_2019-3-6_8-53-32.png

I realized some of my mistakes in matlab. The above is the fft of the signal when passed through the rrc filter function.
For LO noise I suppressed it by adding a filter capacitor on the RF line but the output is much reduced. maybe i have to increase the gain factor.
 

cariban

Joined Aug 14, 2018
69
View attachment 171636
View attachment 171638
View attachment 171640

I realized some of my mistakes in matlab. The above is the fft of the signal when passed through the rrc filter function.
For LO noise I suppressed it by adding a filter capacitor on the RF line but the output is much reduced. maybe i have to increase the gain factor.
So you have measured the LO and found spurs close to the carrier? If yes, the spurs are from PLL and possible to be removed. Just trace back where the spurs origin. Remove the spurs from the output signal is very difficult and generally not an engineering solution.
 

cariban

Joined Aug 14, 2018
69
View attachment 171636
View attachment 171638
View attachment 171640

I realized some of my mistakes in matlab. The above is the fft of the signal when passed through the rrc filter function.
For LO noise I suppressed it by adding a filter capacitor on the RF line but the output is much reduced. maybe i have to increase the gain factor.
Just one comment about the spectrum plotting. It is better to use logarithm for Y-axis. Also use many times averaging (for example 100-1000) if the spectrum is not smooth enough.
 
Top